View ADSP-21161NYCAZ110_6516593.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sharc and the sharc logo are registered trademarks of analog devices, inc. sharc processor adsp-21161n rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com summary high performance 32-bit dspapplications in audio, medi- cal, military, wireless communications, graphics, imaging, motor-control, and telephony super harvard architecturef our independent buses for dual data fetch, instruction fetch, and nonintrusive zero- overhead i/o code compatible with all other sharc family dsps single-instruction multiple-data (simd) computational archi- tecturetwo 32-bit ieee floating-point computation units, each with a multiplier, alu, shifter, and register file serial ports offer i 2 s support via 8 programmable and simul- taneous receive or transmit pins, which support up to 16 transmit or 16 receive channels of audio integrated peripheralsintegrat ed i/o processor, 1m bit on- chip dual-ported sram, sdra m controller, glueless multi- processing features, and i/o ports (serial, link, external bus, spi, and jtag) adsp-21161n supports 32-bit fixed, 32-bit float, and 40-bit floating-point formats 100 mhz/110 mhz core instruction rate single-cycle instruction exec ution, including simd opera- tions in both computational units up to 660 mflops peak and 440 mflops sustained performance 225-ball 17 mm ?? 17 mm csp_bga package figure 1. adsp-21161n functional block diagram alu mult data register file (pey) 16 u 40-bit barrel shifter barrel shifter alu data register file (pex) 16 u 40-bit timer instruction cache 32 u 48-bit dag1 8 u 4 u 32 program sequencer 32 pm address bus dm address bus 32 bus connect (px) pm data bus dm data bus 64 64 core processor spi ports (1) serial ports (4) link ports (2) dma controller 5 16 20 4 iop registers (memory mapped) control, status, & data buffers i/o processor two independent dual-ported blocks addr data data data addr addr data addr processor port i/o port b l oc k 0 b l o c k 1 dual-ported sram host port addr bus mux multiprocessor interface data bus mux 32 24 external port 6 12 8 jtag test and emulation gpio flags sdram controller ioa 18 iod 64 dag2 8 u 4 u 32 mult s
rev. c | page 2 of 60 | january 2013 adsp-21161n table of contents summary ............................................................... 1 general description ................................................. 3 adsp-21161n family co re architecture . ................... 3 adsp-21161n memory and i/o interface features ....... 5 development tools ............................................... 9 additional information ........................................ 10 related signal chains .......................................... 10 pin function descriptions ....................................... 11 boot modes ....................................................... 16 specifications ........................................................ 17 operating conditions .......................................... 17 electrical characteristics ....................................... 18 package information ........................................... 19 absolute maximum ratings ................................... 19 esd caution ...................................................... 19 timing specifications ........................................... 19 power dissipation ............................................... 20 output drive currents ......................................... 54 test conditions .................................................. 54 environmental conditions .................................... 55 225-ball csp_bga ball configurations ... .................... 56 outline dimensions ................................................ 58 surface-mount design .......................................... 58 ordering guide ..................................................... 58 revision history 1/13rev. b to rev. c updated development tools ...................................... 9 added section, related signal chains .......................... 10 added footnote 3 to table 16 in memory read bus master .................................... 27
adsp-21161n rev. c | page 3 of 60 | january 2013 general description the adsp-21161n sharc ? dsp is a low cost derivative of the adsp-21160 featuring analog devices super harvard archi- tecture. easing portability, the adsp-21161n is source code compatible with the adsp-21 160 and with firs t generation adsp-2106x sharc processors in sisd (single-instruction, single-data) mode. like ot her sharc dsps, the adsp- 21161n is a 32-bit proc essor that is optimi zed for high perfor- mance dsp applications. the adsp-21161n includes a 100 mhz or 110 mhz core, a dual-ported on-chip sram, an integrated i/o processor with multiprocessing support, and multiple internal buses to eliminate i/o bottlenecks. as was first offered in the adsp-21160, the adsp-21161n offers a single-instruction mult iple-data (simd) architecture. using two computational unit s (adsp-2106x sharc proces- sors have one), the adsp -21161n can double cycle performance versus the adsp-2106x on a range of dsp algorithms. fabricated in a state of the ar t, high speed, low power cmos process, the adsp-21161n has a 10 ns or 9 ns instruction cycle time. with its simd computat ional hardware running at 110 mhz, the adsp-21161n can pe rform 660 million floating- point operations per second. table 1 shows performance bench- marks for the adsp-21161n. these benchmarks provide single -channel extrapolations of measured dual-channel processing performance. for more information on benchmarking and optimizing dsp code, for both single and dual-channel pr ocessing, see the analog devices inc. website. the adsp-21161n continues shar cs industry-leading stan- dards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. these features include a 1m bit dual ported sram memory, host pro- cessor interface, i/o processor that supports 14 dma channels, four serial ports, two link po rts, sdram controller, spi inter- face, external parallel bus, and glueless multiprocessing. the block diagram of the adsp-21161n on page 1 illustrates the following architectural features: ? two processing elements, each made up of an alu, multi- plier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer wi th instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core every core proces- sor cycle ?interval timer ?on-chip sram (1m bit) ? sdram controller for glueless interface to sdrams ? external port that supports: ? interfacing to off-ch ip memory peripherals ? glueless multiprocessing support for six adsp-21161n sharcs ? host port read/write of iop registers ? dma controller ? four serial ports ?two link ports ? spi compatible interface ? jtag test access port ? 12 general-purpose i/o pins figure 2 shows a typical single-pro cessor system. a multipro- cessing system appears in figure 5 on page 8 . adsp-21161n family core architecture the adsp-21161n includes the follo wing architectural features of the adsp-2116x family co re. the adsp-21161n is code compatible at the assembly level with the adsp-21160, adsp-21060, adsp-21061, adsp-21062, and adsp-21065l. simd computational engine the adsp-21161n contains two co mputational processing ele- ments that operate as a single-instruction multiple-data (simd) engine. the processing elements are referred to as pex and pey, and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing ele- ments, but each processing elem ent operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory an d the processing elements. table 1. benchmarks benchmark algorithm 100 mhz instruction rate 110 mhz instruction rate 1024 point complex fft (radix 4, with reversal) 92 s 83.6 s fir filter (per tap) 5 ns 4.5 ns iir filter (per biquad) 20 ns 18.18 ns matrix multiply (pipelined) [3 ?? 3] ? [3 ?? 1] 45 ns 40.9 ns [4 ?? 4] ? [4 ?? 1] 80 ns 72.72 ns divide (y/x) 60 ns 54.54 ns inverse square root 40 ns 36.36 ns dma transfers 800m bytes/s 880m bytes/s
rev. c | page 4 of 60 | january 2013 adsp-21161n when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the regis- ter file. simd is supported only for inte rnal memory acce sses and is not supported for off-chip accesses. independent, paralle l computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform single-cycle instructions. the three units with in each processing element are arranged in parallel, maximizi ng computational throughput. single multifunction instruct ions execute parallel alu and multiplier operations. in si md mode, the parallel alu and multiplier operations occur in both processing elements. these computation units support ieee 32-bit single-precision float- ing-point, 40-bit extended prec ision floating-point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is contained in each pro- cessing element. the register fi les transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined with the sharc enhanced harvard architecture, allow unconstrained data flow between computa- tion units and internal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. single-cycle fetch of instruction and four operands the adsp-21161n features an en hanced harvard architecture in which the data memory (dm) bus transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 2 ). with the adsp-21161ns separate program and data memory buses and on-chip instruction cache, the proces- sor can simultaneously fetch four operands (two over each data bus) and an instruction (from th e cache), all in a single cycle. figure 2. system diagram dma device (optional) data clkout dmar2-1 dmag2-1 addr data ho s t proce ss or interface (optional) 3 12 clock clkin xtal irq2-0 2 clk_cfg1-0 eboot lboot flag11-0 timexp clkdbl re s et jtag 7 s bt s ad s p-21161n bm s link device s (2 max) (optional) lxclk lxack lxdat7-0 s clk0 d0b d0a f s 0 s erial device (optional) c s boot eprom (optional) addr memory and peripheral s (optional) oe data c s rd ra s ack br6-1 rpba id2-0 pa hbg hbr s dwe m s3 -0 wr data47-16 data addr c s ack we addr2 3 -0 d a t a c o n t r o l a d d r e s s br s t s dram (optional) s clk1 d1b d1a f s 1 s erial device (optional) s clk2 d2b d2a f s 2 s erial device (optional) s clk 3 d 3 b d 3 a f s3 s erial device (optional) s piclk mi s o mo s i s pid s s pi compatible device (ho s tor s lave) (optional) data ca s ra s dqm we addr c s a10 cke clk dqm ca s redy s dcke s da10 s dclk1-0 r s tout
adsp-21161n rev. c | page 5 of 60 | january 2013 instruction cache the adsp-21161n includes an on -chip instruction cache that enables three-bus operat ion for fetching an instruction and four data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache enables full-speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators with hardware circular buffers the adsp-21161ns two data addr ess generators (dags) are used for indirect addressing an d implementing circular data buffers in hardware. circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the adsp-21161n con- tain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automatically handle address pointer wrap-around, reduce overhead, increase performance, and simplify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations, for concise programming. for example, the adsp-21161n can conditionally execute a multiply, an add, and a subtract in both processing elements, while branching, all in a single instruction. adsp-21161n memory and i/o interface features the adsp-21161n adds the following architectural features to the adsp-2116x family core. dual-ported on-chip memory the adsp-21161n contains one megabit of on-chip sram, organized as two blocks of 0.5m bits ( figure 3 ). each block can be configured for different combinations of code and data stor- age. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor. the dual-ported memory in comb ination with three separate on-chip buses allow two data tr ansfers from the core and one from the i/o processor, in a si ngle cycle. on the adsp-21161n, the memory can be configured as a maximum of 32k words of 32-bit data, 64k words of 16-bi t data, 21k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on -chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. whil e each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the dm bus for transfers, and the other block stores instructions and data using the pm bus for transfers. using the dm bus and pm bus, with one dedicated to each memory block, assures si ngle-cycle execution with two data transfers. in this case, the instruction must be available in the cache. off-chip memory and peripherals interface the adsp-21161ns external port provides the processors interface to off-chip memory and peripherals. the 62.7-m word off-chip address space (254.7-m wo rd if all sdram) is included in the adsp-21161ns unified ad dress space. the separate on- chip busesfor pm addresses, pm data, dm addresses, dm data, i/o addresses, and i/o dataare multiplexed at the exter- nal port to create an external system bus with a single 24-bit address bus and a single 32-bit data bus. every access to external memory is based on an address that fetches a 32-bit word. when fetching an instruction from external memory, two 32-bit data locations are being acce ssed for packed instructions. unused link port lines can also be used as additional data lines data15Cdata0, allowing single -cycle execution of instruc- tions from external memory, at up to 110 mhz. figure 4 shows the alignment of various ac cesses to external memory. the external port supports asynchronous, synchronous, and synchronous burst accesses. sy nchronous burst sram can be interfaced gluelessly. the adsp -21161n also can interface glue- lessly to sdram. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. the adsp-21161n pro- vides programmable memory wait states and external memory acknowledge controls to allo w interfacing to memory and peripherals with variable ac cess, hold, and disable time requirements. sdram interface the sdram interface enables the adsp-21161n to transfer data to and from synchronous dram (sdram) at the core clock frequency or at one-half the core clock frequency. the synchronous approach, coupled with the core clock frequency, supports data transfer at a high throughputup to 440m bytes/s for 32-bit tran sfers and up to 660m bytes/s for 48-bit transfers. the sdram interface provides a glueless interface with stan- dard sdrams16mb, 64mb, 128mb, and 256mb and includes options to support ad ditional buffers between the adsp-21161n and sdram. th e sdram interface is extremely flexible and provides capability for connecting sdrams to any one of the ad sp-21161ns four external mem- ory banks, with up to all four banks mappe d to sdram. systems with several sdram devi ces connected in parallel may require buffering to meet overall system timing requirements. the adsp-21161n supports pipelini ng of the address and con- trol signals to enable such buffe ring between itself and multiple sdram devices. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test acce ss port of the adsp-21161n processor to monitor and contro l the target board processor during emulation. analog devices dsp tools product line of
rev. c | page 6 of 60 | january 2013 adsp-21161n jtag emulators provides emulat ion at full processor speed, allowing inspection and modifica tion of memory, registers, and processor stacks. the processor s jtag interface ensures that the emulator will not affect targ et system load ing or timing. for complete information on sharc analog devices dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide. for detailed infor- mation on the interfacing of analog devices jtag emulators with analog devices dsp products with jtag emulation ports, please refer to engineer to engineer note ee-68: analog devices jtag emulation technical reference . both of these documents can be found on the analog devices website. dma controller the adsp-21161ns on-chip dm a controller enables zero- overhead data transfers without processor intervention. the dma controller operates indepe ndently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between th e adsp-21161ns internal mem- ory and external memory, external peripherals, or a host processor. dma transfers can also occur between the adsp- 21161ns internal memory and its serial ports, link ports, or the spi-compatible (serial peripheral interface) port. external bus packing and unpacking of 32-, 48-, or 64-bit words in internal memory is performed during dm a transfers from either 8-, 16-, or 32-bit wide external me mory. fourteen channels of dma are available on the adsp-21161ntwo are shared between the spi interface and the link ports, eight via the serial ports, and four via the processor s external port (for host pro- cessor, other adsp-21161ns, memory, or i/o transfers). programs can be downloaded to the adsp-21161n using dma transfers. asynchrono us off-chip peripherals can control two dma channels using dma request/grant lines (dmar2C1 , dmag2C1 ). other dma features incl ude interrupt generation upon completion of dma transfers, and dma chaining for automatic linked dma transfers. figure 3. memory map 0x000a 0000 - 0x000a7fff(blk1) 0x0002 8 000 - 0x0002 9fff (blk 1) 0x0005 0000 - 0x0005 3 fff (blk 1) 0x0010 0000 - 0x0011 ffff 0x0004 0000 - 0x0004 3 fff (blk 0) 0x000 8 0000 - 0x000 8 7fff (blk 0) 0x0012 0000 - 0x001 3 ffff 0x0014 0000 - 0x0015 ffff 0x0016 0000 - 0x0017 ffff 0x001a 0000 - 0x001b ffff 0x0000 0000 - 0x0001 ffff 0x0002 0000 - 0x0002 1fff (blk 0) 0x0020 0000 bank 1 m s 0 bank 2 m s 1 bank 3 m s 2 m s3 iop regi s ter s long word addre ss ing s hort word addre ss ing normal word addre ss ing addre ss bank 0 0x0 3 ff ffff ( s dram) 0x00ff ffff (non- s dram) 0x0400 0000 0x07ff ffff ( s dram) 0x04ff ffff (non- s dram) 0x0 8 00 0000 0x0bff ffff ( s dram) 0x0 8 ff ffff (non- s dram) 0x0c00 0000 0x0fff ffff ( s dram) 0x0cff ffff (non- s dram) note: bank s ize s are fixed 0x001 8 0000 - 0x0019 ffff internal memory s pace multiproce ss or memory s pace addre ss iop regi s ter s of ad s p-21161n with id = 001 iop regi s ter s of ad s p-21161n with id = 010 iop regi s ter s of ad s p-21161n with id = 011 iop regi s ter s of ad s p-21161n with id = 100 iop regi s ter s of ad s p-21161n with id = 101 iop regi s ter s of ad s p-21161n with id = 110 re s erved 0 x 001c 0000 0 x 001f ffff external memory s pace
adsp-21161n rev. c | page 7 of 60 | january 2013 multiprocessing the adsp-21161n offers powerf ul features tailored to multiprocessing dsp systems. the external port and link ports provide integrated gluele ss multiprocessing support. the external port supports a unified address space (see figure 3 ) that enables direct interpro cessor accesses of each adsp- 21161ns internal memory-mapped (i/o processor) registers. all other internal memory can be indirectly accessed via dma transfers initiated via the programming of the iop dma parameter and control registers. distributed bus arbitration logic is included on-chip for si mple, glueless connection of sys- tems containing up to six ad sp-21161ns and a host processor ( figure 5 ). master processor change over incurs only one cycle of overhead. bus arbitration is selectable as either fixed or rotat- ing priority. bus lock enables indivisible read-modify-write sequences for semaphores. a vect or interrupt is provided for interprocessor commands. using an instruction rate of 110 mhz, maximum throughput for interprocessor data trans- fer is 440m bytes/s over the external port. two link ports provide a second method of multiprocessing communications. each link port can support communications to another adsp-21161n. th e adsp-21161n, running at 110 mhz, has a maximum throughput for interprocessor com- munications over the links of 220m bytes/s. the link ports and cluster multiprocessing can be used concurrently or independently. link ports the adsp-21161n features two 8- bit link ports that provide additional i/o capabilities. with the capability of running at 110 mhz, each link port can su pport 110m bytes/s. link port i/o is especially useful for point-to-point interprocessor com- munication in multiprocessing systems. the link ports can operate independently and simultaneously, with a maximum data throughput of 220m bytes/s. link port data is packed into 48- or 32-bit word s and can be directly read by the core proces- sor or dma-transferre d to on-chip memory. each link port has its own double-buffered inpu t and output registers. clock/acknowledge handshaking controls link port transfers. transfers are programmable as either transmit or receive. serial ports the adsp-21161n features four sy nchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. ea ch serial port is made up of two data lines, a clock and frame sync. the data lines can be programmed to either transmit or receive. the serial ports operate at up to half the clock rate of the core, providing each with a maximum data rate of 55m bit/s. the serial data pins are programmable as either a transmitter or receiver, providing greater flexibility for serial communications. serial port data can be automatically transferred to and from on-chip memory via a dedicated dma. each of the serial ports features a time division multiplex (tdm) multichannel mode, where two serial ports are tdm transmitters and two serial ports are tdm receivers (sport0 rx paired with sport2 tx, sport1 rx paired with sport3 tx ). each of the serial ports also support the i 2 s protocol (an industry standard interface commonly used by audio codecs , adcs and dacs), with two data pins, allowing four i 2 s channels (using two i 2 s stereo devices) per serial port, with a maximum of up to 16 i 2 s chan- nels. the serial ports permit little-endian or big-endian transmission formats an d word lengths selectable from 3 bits to 32 bits. for i 2 s mode, data-word lengths are selectable between 8 bits and 32 bits. serial ports offer selectable synchronization and transmit modes as well as optional -law or a-law com- panding. serial port clocks and frame syncs can be internally or externally generated. serial peripheral (compatible) interface serial peripheral interface (spi) is an industry standard syn- chronous serial link, en abling the adsp-21161n spi- compatible port to communicate with other spi-compatible devices. spi is a 4-wire interface consisting of two data pins, one device select pin, and one clock pin. it is a full-duplex synchro- nous serial interface, supportin g both master and slave modes. the spi port can operate in a multimaster environment by interfacing with up to four othe r spi-compatible devices, either acting as a master or slave device. the adsp-21161n spi-com- patible peripheral im plementation also fe atures programmable baud rate and clock phase/po larities. the adsp-21161n spi- compatible port uses open drai n drivers to support a multimas- ter configuration and to avoid data contention. host processor interface the adsp-21161n host interface enables easy connection to standard 8-bit, 16-bit, or 32-bit microproce ssor buses with little additional hardware required. the host interface is accessed through the adsp-21161ns extern al port. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host proces- sor requests the adsp-21161ns ex ternal bus with the host bus request (hbr ), host bus grant (hbg ), and chip select (cs) sig- nals. the host can directly re ad and write the internal iop registers of the adsp-21161n, an d can access the dma channel figure 4. external data alignment options da t a 1 5C0 15 8 70 l1data7C0 dat a15- 8 l0data7C0 da ta7C0 16-bit packed dma data 16-bit packed in s truc- tion execution float or fixed, d 3 1C d0 , 3 2-bit pa cked 3 2-bit pa cked in s truc- tion ex tra da ta li ne s data15C0 ar e only acce ss ible if link port s ar e d i s abled. enab le the s e additional data l ink s by s elect- ing ipac k 1 C 0 = 0 1in s s c o n. 4 8 -bit in s truct ion fetch (no packing) 47 4 0 3 9 3 2 3 1242 3 16 data4 7C1 6 8 -bit packed dma d ata 8 -bit packed in s truction execution prom bo o t note:
rev. c | page 8 of 60 | january 2013 adsp-21161n setup and message registers. dma setup via a host would allow it to access any internal memo ry address via dma transfers. vector interrupt support provides efficient execution of host commands. the host processor interface can be used in either multiproces- sor or single processor shar c systems. for multiprocessor systems, host access to the sharc requires address pins addr17, addr18, addr19, and addr20 to be driven low. it is not enough to tie these pi ns to ground through a resistor figure 5. shared memory multiprocessing system ack oe addr data c s we global memory and peripheral s (optional) c o n t r o l ad s p-21161n #1 addr2 3 -0 control ad s p-21161n # 3 id2-0 re s et clkin 3 ad s p-21161n #4 clock addr data s dram (optional) c s addr data boot eprom (optional) id2-0 re s et clkin c o n t r o l a d d r e s s d a t a c o n t r o l a d d r e s s d a t a control ad s p-21161n #2 id2-0 re s et clkin 2 1 addr data ho s t proce ss or interface (optional) we ra s ca s dqm clk a10 cke c s data47-16 s dwe ra s ca s dqm s dclk1-0 s da10 s dcke br6-2 rd m s3 -0 s bt s c s ack br1 redy hbg hbr wr bm s addr2 3 -0 re s et data47-16 addr2 3 -0 data47-16
adsp-21161n rev. c | page 9 of 60 | january 2013 (for example 10k ohm). these pins must be driven low with a strong enough drive strength (10C50 ohms) to overcome the sharc keeper latches present on these pins. if the drive strength provided is not strong enough, data access failures can occur. for single processor sharc syst ems using this host access fea- ture, address pins addr17, addr18, addr19, and addr20 may be tied low (for example through a 10k ohm resistor), driven low by a buffer/driver, or left floating. any of these options is sufficient. general-purpose i/o ports the adsp-21161n also contains 12 programmable, general purpose i/o pins that can function as either input or output. as output, these pins can signal peri pheral devices; as input, these pins can provide the test for conditional branching. program booting the internal memory of the adsp-21161n can be booted at system power-up from either an 8-bit eprom, a host processor, the spi interface, or through one of the link ports. selection of the boot source is controlled by the boot memory select (bms ), eboot (eprom boot), and link/host boot (lboot) pins. 8-, 16-, or 32-bit host processors can also be used for booting. phase-locked loop and crystal double enable the adsp-21161n uses an on-chip phase-locked loop (pll) to generate the internal clock for the core. the clk_cfg1C0 pins are used to select ratios of 2:1, 3:1, and 4:1. in addition to the pll ratios, the clkdbl pin can be used for more clock ratio options. the (1 ? /2 ? clkin) rate set by the clkdbl pin determines the rate of the pll input clock and the rate at which the external port operat es. with the combination of clk_cfg1C0 and clkdbl , ratios of 2:1, 3:1, 4:1, 6:1, and 8:1 between the core and clkin are supported. see also figure 8 on page 20 . power supplies the adsp-21161n has separate power supply connections for the analog (av dd /agnd), internal (v ddint ), and external (v ddext ) power supplies. the internal and analog supplies must meet the 1.8 v requirement. the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same supply. note that the analog supply (av dd ) powers the adsp-21161ns clock generator pll. to produce a stable clock, provide an external circuit to filter the power input to the av dd pin. place the filter as close as po ssible to the pin. the av dd filter circuit shown in figure 6 must be added for each adsp-21161n in the multiprocessor system. to prevent noise coupling, use a wide trace for the analog ground (agnd) signal and install a decou- pling capacitor as close as possible to the pin. development tools analog devices supports its proce ssors with a complete line of software and hardware development tools, including integrated development environments (which include crosscore ? embed- ded studio and/or visualdsp++ ? ), evaluation products, emulators, and a wide variety of software add-ins. integrated development environments (ides) for c/c++ software writing and editing, code generation, and debug support, analog devices offers two ides. the newest ide, crosscore embe dded studio, is based on the eclipse tm framework. supporting most analog devices proces- sor families, it is the ide of choice for future processors, including multicore devices. crosscore embedded studio seamlessly integrates available so ftware add-ins to support real time operating systems, file systems, tcp/ip stacks, usb stacks, algorithmic software modules, and evaluation hardware board support packages. for more information visit www.analog.com/cces . the other analog devices ide, visualdsp++, supports proces- sor families introduced prior to the release of crosscore embedded studio. this ide incl udes the analog devices vdk real time operating system and an open source tcp/ip stack. for more information visit www.analog.com/visualdsp . note that visualdsp++ will not suppo rt future analog devices processors. ez-kit lite evaluation board for processor evaluation, analog devices provides wide range of ez-kit lite ? evaluation boards. incl uding the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. also available are various ez-extenders ? , which are daughter cards delivering additional specialized functionality, including audio and video processing. for more information visit www.analog.com and search on ezkit or ezextender. ez-kit lite evaluation kits for a cost-effective way to lear n more about developing with analog devices processors, analog devices offer a range of ez- kit lite evaluation kits. each evaluation kit includes an ez-kit lite evaluation board, directions for downloading an evaluation version of the available ide(s), a usb cable, and a power supply. the usb controller on the ez-kit lite board connects to the usb port of the users pc, enab ling the chosen ide evaluation suite to emulate the on-board pr ocessor in-circuit. this permits the customer to download, execut e, and debug programs for the ez-kit lite system. it also su pports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operation. with the full version of cross- figure 6. analog power (av dd ) filter circuit 10 v ddint 0.1 f 0.01 f agnd av dd
rev. c | page 10 of 60 | january 2013 adsp-21161n core embedded studio or visualdsp++ installed (sold separately), engineers can deve lop software for supported ez- kits or any custom system util izing supported analog devices processors. software add-ins for cr osscore embedded studio analog devices offers software add-ins which seamlessly inte- grate with crosscore embedded stud io to extend its capabilities and reduce development time. add-ins include board support packages for evaluation hardwa re, various middleware pack- ages, and algorithmic modules. documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through th e crosscore embedded studio ide once the add-in is installed. board support packages for evaluation hardware software support for the ez-kit lite evaluation boards and ez- extender daughter cards is prov ided by software add-ins called board support packages (bsps). the bsps contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. a downlo ad link for a specific bsp is located on the web page for the associated ez-kit or ez- extender product. the link is found in the product download area of the product web page. middleware packages analog devices separately offers middleware add-ins such as real time operating systems, file systems, usb stacks, and tcp/ip stacks. for more information see the following web pages: ? www.analog.com/ucos3 ? www.analog.com/ucfs ? www.analog.com/ucusbd ? www.analog.com/lwip algorithmic modules to speed development, analog de vices offers add-ins that per- form popular audio and video processing algorithms. these are available for use with both cr osscore embedded studio and visualdsp++. for more information visit www.analog.com and search on blackfin software modules or sharc software modules. designing an emulator-compatible dsp board (target) for embedded system test and de bug, analog devices provides a family of emulators. on each jtag dsp, analog devices sup- plies an ieee 1149.1 jtag test access port (tap). in-circuit emulation is facilitated by use of this jtag interface. the emu- lator accesses the processors internal features via the processors tap, allowing the de veloper to load code, set break- points, and view variables, memory, and registers. the processor must be halted to se nd data and commands, but once an operation is completed by the emulator, the dsp system is set to run at full speed with no im pact on system timing. the emu- lators require the target board to include a header that supports connection of the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connection s, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a general overview of the adsp-21161n architecture and fu nctionality. for detailed information on the adsp-2116x fa mily core arch itecture and instruction set, refer to the adsp-21161 sharc dsp hardware reference and the adsp-21160 sharc dsp instruction set reference . related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http://www.analog.com/signal chains ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques
adsp-21161n rev. c | page 11 of 60 | january 2013 pin function descriptions adsp-21161n pin definiti ons are listed below. inputs identified as synchronous (s) must meet ti ming requirements with respect to clkin (or with respect to tc k for tms, tdi). inputs iden- tified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). tie or pull unused inputs to v ddext or gnd, except for the following: ? addr23C0, data47C0, brst, clkout (note: these pins have a logic-level ho ld circuit enabled on the adsp-21161n dsp with id2C0 = 00x.) ?pa , ack, rd , wr , dmarx , dmagx , (id2C0 = 00x) (note: these pins have a pull-up enabled on the adsp-21161n dsp with id2C0 = 00x.) ? lxclk, lxack, lxdat7C0 (lxpdrde = 0) (note: see link port buffer control regi ster bit definitions in the adsp-21161n sharc dsp hardware reference. ) ? dxa, dxb, sclkx, spiclk, miso, mosi, emu , tms,trst , tdi (note: these pins have a pull-up.) the following symbol s appear in the type column of table 2 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state (when sbts is asserted or when the adsp-21161n is a bus slave). unlike previous sharc proc essors, the adsp-21161n con- tains internal series resi stance equivalent to 50 ? on all input/output drivers except the clkin and xtal pins. therefore, for traces lo nger than six inches, external series resis- tors on control, data, clock, or frame sync pins are not required to dampen reflections from tran smission line effects for point- to-point connections. however, for more complex networks such as a star configuration, series termination is still recommended. table 2. pin function descriptions pin type function addr23C0 i/o/t external bus address. the adsp-21161n outputs addresses for external memory and peripherals on these pins. in a multiprocessor system the bus master outputs addresses for read/writes of the iop registers of other adsp-21161ns while all other internal memory resour ces can be accessed indirectly via dma control (that is, accessing iop dma parameter registers). the adsp-2 1161n inputs addresses when a host processor or multiprocessing bus master is reading or writing its iop registers. a keeper latch on the dsps addr23-0 pins maintains the input at the level it was last driven. this latch is only enabled on the adsp-21161n with id2C0=00x. data47C16 i/o/t external bus data. the adsp-21161n inputs and outputs data and instructions on these pins. pull-up resistors on unused data pins are not necessary. a ke eper latch on the dsps data47C16 pins maintains the input at the level it was last driven. this latch is only enabled on the adsp-21161n with id2C0=00x. note: data15C8 pins (multiplexed with l1dat7C0) can also be used to extend the data bus if the link ports are disabled and will not be used. in addition, data7C0 pins (multiplexed with l0dat7C0) can also be used to extend the data bus if the link ports are not used. this enables execution of 48-bit instructions from external sbsram (system clock speed-external port), sram (system clock speed-external port) and sdram (core clock or one-half the core clock speed). the ipackx instruction packing mode bits in syscon should be set correctly (ipack1C0=0x1) to enable this full instruction wi dth/no-packing mode of operation. ms3C0 i/o/t memory select lines. these outputs are asserted (low) as chip selects for the corresponding banks of external memory. memory bank sizes are fixed to 16 m words for non-sdram and 64m words for sdram. the ms3C0 outputs are decoded memory address lines. in asynchronous access mode, the ms3C0 outputs transition with the other address outputs . in synchronous access modes, the ms3C0 outputs assert with the other address lines; however, they deassert after the first clkin cycle in which ack is sampled asserted. in a multiprocessor system, the msx signals are tracked by slave sharcs. rd i/o/t memory read strobe. rd is asserted whenever adsp-21161n reads a word from external memory or from the iop registers of other adsp-21161ns. external devices, including other adsp-21161ns, must assert rd for reading from a word of the adsp-21161n iop register memory. in a multiprocessing system, rd is driven by the bus master. rd has a 20 k ? internal pull-up resistor that is enabled for dsps with id2C0=00x. wr i/o/t memory write low strobe. wr is asserted when adsp-21161n writes a word to external memory or iop registers of other adsp-21161ns. external devices must assert wr for writing to adsp-21161n iop registers. in a multiprocessing system, the bus master drives wr. wr has a 20 k ? internal pull-up resistor that is enabled for dsps with id2C0=00x.
rev. c | page 12 of 60 | january 2013 adsp-21161n brst i/o/t sequential burst access. brst is asserted by adsp-21161n to indicate that data associated with consecutive addresses is being read or written. a slave device samples the initial address and increments an internal address counter after each transfer. the incremented address is not pipelined on the bus. a master adsp- 21161n in a multiprocessor environment can read slave ex ternal port buffers (epbx) using the burst protocol. brst is asserted after the initial access of a burst transfer. it is asserted for every cycle after that, except for the last data request cycle (denoted by rd or wr asserted and brst negated). a keeper latch on the dsps brst pin maintains the input at the level it was last driven. this latch is only enabled on the adsp-21161n with id2C0=00x. ack i/o/s memory acknowledge. external devices can de-assert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers , or other peripherals to hold off completion of an external memory access. the adsp-21161n deasserts ack as an output to add wait states to a synchronous access of its iop registers. ack has a 20 k ? internal pull-up resistor that is enabled during reset or on dsps with id2C0=00x. sbts i/s suspend bus and three-state. external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high impedance state fo r the following cycle. if the adsp-21161n attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is deasserted. sbts should only be used to recove r from host processor/adsp-21161n deadlock. cas i/o/t sdram column access strobe. in conjunction with ras , msx , sdwe , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. ras i/o/t sdram row access strobe. in conjunction with cas , msx , sdwe , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. sdwe i/o/t sdram write enable. in conjunction with cas , ras , msx , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. dqm o/t sdram data mask. in write mode, dqm has a latency of ze ro and is used during a precharge command and during sdram power-up initialization. sdclk0 i/o/s/t sdram clock output 0. clock for sdram devices. sdclk1 o/s/t sdram clock output 1. additional clock for sdram devices. for systems with multiple sdram devices, handles the increased clock load requirements, eliminating need of off-chip clock buffers. either sdclk1 or both sdclkx pins can be three-stated. sdcke i/o/t sdram clock enable. enables and disables the clk signal. for details, see the data sheet supplied with the sdram device. sda10 o/t sdram a10 pin. enables applications to refresh an sdram in parallel with a non-sdram accesses or host accesses. this pin replaces the dsps a10 pin only during sdram accesses. irq2C0 i/a interrupt request lines. these are sampled on the rising edge of clkin and may be either edge-triggered or level-sensitive. flag11C0 i/o/a flag pins. each is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. timexp o timer expired. asserted for four core clock cycles when the timer is enabled and tcount decrements to zero. hbr i/a host bus request. must be asserted by a host processor to re quest control of the adsp-21161ns external bus. when hbr is asserted in a multiprocessing system, the adsp-21161n that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the adsp-21161n pl aces the address, data, select, and strobe lines in a high impedance state. hbr has priority over all adsp-21161n bus requests (br6C1 ) in a multipro- cessing system. hbg i/o host bus grant. acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the adsp-21161n until hbr is released. in a multiprocessing system, hbg is output by the adsp-21161n bus master and is monitored by all others. after hbr is asserted, and before hbg is given, hbg will float for 1 t ck (1 clkin cycle). to avoid erroneous grants, hbg should be pulled up with a 20 k ? to 50 k ? external resistor. cs i/a chip select. asserted by host processor to select the adsp-21161n. table 2. pin function descriptions (continued) pin type function
adsp-21161n rev. c | page 13 of 60 | january 2013 redy o (o/d) host bus acknowledge . the adsp-21161n deasserts redy (low) to add wait states to a host access of its iop registers when cs and hbr inputs are asserted. dmar1 i/a dma request 1 (dma channel 11). asserted by external port devices to request dma services. dmar1 has a 20 k ? internal pull-up resistor that is enabled for dsps with id2C0=00x. dmar2 i/a dma request 2 (dma channel 12). asserted by external port devices to request dma services. dmar2 has a 20 k ? internal pull-up resistor that is enabled for dsps with id2C0=00x. dmag1 o/t dma grant 1 (dma channel 11). asserted by adsp-21161n to indicate that the requested dma starts on the next cycle. driven by bus master only. dmag1 has a 20 k ? internal pull-up resistor that is enabled for dsps with id2C0=00x. dmag2 o/t dma grant 2 (dma channel 12). asserted by adsp-21161n to indicate that the requested dma starts on the next cycle. driven by bus master only. dmag2 has a 20 k ? internal pull-up resistor that is enabled for dsps with id2C0=00x. br6C1 i/o/s multiprocessing bus requests . used by multiprocessing adsp-21161ns to arbitrate for bus mastership. an adsp-21161n only drives its own brx line (corresponding to the value of its id2C0 inputs) and monitors all others. in a multiprocessor system with le ss than six adsp-21161ns, the unused brx pins should be pulled high; the processor's own brx line must not be pulled high or low because it is an output. bmstr o bus master output . in a multiprocessor system, indicates whet her the adsp-21161n is current bus master of the shared external bus. the adsp-21161n drives bmst r high only while it is the bus master. in a single- processor system (id=000), the processor drives this pin high. this pin is used for debugging purposes. id2C0 i multiprocessing id . determines which multiprocessing bus request (br6 Cbr1 ) is used by adsp-21161n. id=001 corresponds to br1 , id=010 corresponds to br2 , and so on. use id=000 or id=001 in single- processor systems. these lines are a system configuratio n selection that should be hardwired or only changed at reset. rpba i/s rotating priority bus arbitration select . when rpba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed priori ty is selected. this signal is a system configuration selection that must be set to the same value on ever y adsp-21161n. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-21161n. pa i/o/t priority access . asserting its pa pin enables an adsp-21161n bus slave to interrupt background dma transfers and gain access to the external bus. pa is connected to all adsp-211 61ns in the system. if access priority is not required in a system, the pa pin should be left unconnected. pa has a 20 k ? internal pull-up resistor that is enabled for dsps with id2C0=00x. dxa i/o data transmit or receive channel a (serial ports 0, 1, 2, 3). each dxa pin has an internal pull-up resistor. bidirectional data pin. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. dxb i/o data transmit or receive channel b (serial ports 0, 1, 2, 3). each dxb pin has an internal pull-up resistor. bidirectional data pin. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. sclkx i/o transmit/receive serial clock (serial ports 0, 1, 2, 3). each sclk pin has an internal pull-up resistor. this signal can be either internally or externally generated. fsx i/o transmit or receive frame sync (serial ports 0, 1, 2, 3). the frame sync pulse initiates shifting of serial data. this signal is either generated internally or externally. it can be active high or low or an early or a late frame sync, in reference to the shifting of serial data. spiclk i/o serial peripheral interface clock signal . driven by the master, this signal controls the rate at which data is transferred. the master may transmit data at a variety of baud rates. spiclk cycles once for each bit trans- mitted. spiclk is a gated clock that is active during data transfers, only for the length of the transferred word. slave devices ignore the serial clock if the slave select in put is driven inactive (high). spiclk is used to shift out and shift in the data driven on the miso and mosi li nes. the data is always shifted out on one clock edge of the clock and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are programmable into the spictl control register and define the transfer format. spiclk has a 50 k ? internal pull-up resistor. table 2. pin function descriptions (continued) pin type function
rev. c | page 14 of 60 | january 2013 adsp-21161n spids i serial peripheral interface slave device select . an active low signal used to enable slave devices. this input signal behaves like a chip select, and is provided by the master device for the slave devices. in multimaster mode spids signal can be asserted to a master device to signal that an error has occurred, as some other device is also trying to be the master device. if asserted low when the device is in master mode, it is considered a multimaster error. for a single-master, multiple-slave configuration where flag3C0 are used, this pin must be tied or pulled high to v ddext on the master device. for adsp-21161n to adsp-21161n spi interaction, any of the master adsp-21161ns flag3C0 pins can be used to drive the spids signal on the adsp-21161n spi slave device. mosi i/o (o/d) spi master out slave . if the adsp-21161n is configured as a master, the mosi pin becomes a data transmit (output) pin, transmitting output data. if the adsp-21161n is configured as a slave, the mosi pin becomes a data receive (input) pin, receiving input data. in an adsp-21161n spi interconnection, the data is shifted out from the mosi output pin of the master and shifted into th e mosi input(s) of the slave(s). mosi has an internal pull-up resistor. miso i/o (o/d) spi master in slave out . if the adsp-21161n is configured as a master, the miso pin becomes a data receive (input) pin, receiving input data. if the adsp-21161n is configured as a slave, the miso pin becomes a data transmit (output) pin, transmitting output data. in an adsp-21161n spi interconnection, the data is shifted out from the miso output pin of the slave and shifted into the miso input pin of the master. miso has an internal pull-up resistor. miso can be configured as o/d by setting the opd bit in the spictl register. note: only one slave is allowed to transmit data at any given time. lxdat7C0 [data15C0] i/o [i/o/t] link port data (link ports 0C1). for silicon revisions 1.2 and higher, each lxdat pin has a keeper latch that is enabled when used as a data pin; or a 20 k ? internal pull-down resistor that is enabled or disabled by the lxpdrde bit of the lctl register. for silicon revisions 0.3, 1.0, an d 1.1 each lxdat pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lxpdrde bit of the lctl register. note: l1dat7C0 are multiplexed wi th the data15C8 pins l0dat7C0 are multiplexed with the data7C0 pins. if link ports are disabled and are not used, these pins can be used as additional data lines for executing instructions at up to the full clock rate from external memory. see data47C16 for more information. lxclk i/o link port clock (link ports 0C1). each lxclk pin has an internal pull-down 50 k ? resistor that is enabled or disabled by the lxpdrde bit of the lctl register. lxack i/o link port acknowledge (link ports 0C1). each lxack pin has an internal pull-down 50 k ? resistor that is enabled or disabled by the lxpd rde bit of the lctl register. eboot i eprom boot select . for a description of how this pin operates, see the table in the bms pin description. this signal is a system configuration selection that should be hardwired. lboot i link boot . for a description of how this pin operates, see the table in the bms pin description. this signal is a system configuration selection that should be hardwired. bms i/o/t boot memory select . serves as an output or input as selected with the eboot and lboot pins (see table 4 ). this input is a system configuration selection that should be hardwired. for host and prom boot, dma channel 10 (epb0) is used. for link boot and spi boot, dma channel 8 is used. three-state only in eprom boot mode (when bms is an output). clkin i local clock in . used in conjunction with xtal. clkin is the adsp-21161n clock input. it configures the adsp- 21161n to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal cl ock generator. connecting the external clock to clkin while leaving xtal unconnected configures the adsp-211 61n to use the external clock source such as an external clock oscillator.the adsp-21161n external por t cycles at the frequency of clkin. the instruction cycle rate is a multiple of the clkin frequency; it is programmable at power-up via the clk_cfg1C0 pins. clkin may not be halted, changed, or operated below the specified frequency. xtal o crystal oscillator terminal 2 . used in conjunction with clkin to enable the adsp-21161ns internal clock oscillator or to disable it to use an external clock source. see clkin. clk_cfg1-0 i core/clkin ratio control . adsp-21161n core clock (instruction cycle) rate is equal to n ? plliclk where n is user selectable to 2, 3, or 4, using the clk_cfg1 C0 inputs. these pins can also be used in combination with the clkdbl pin to generate additional core clock rates of 6 ? clkin and 8 ? clkin (see the clock rate ratios table in the clkdbl description). table 2. pin function descriptions (continued) pin type function
adsp-21161n rev. c | page 15 of 60 | january 2013 clkdbl i crystal double mode enable . this pin is used to enable the 2 ? clock double circuitry, where clkout can be configured as either 1 ? or 2 ? the rate of clkin. this clkin double circuit is primarily intended to be used for an external crystal in conjunction with the internal clock generator and the xtal pin. the internal clock generator when used in conjunction with the xtal pin and an external crystal is designed to support up to a maximum of 27.5 mhz external crystal frequency. clkdbl can be used in xtal mode to generate a 55 mhz input into the pll. the 2 ? clock mode is enabled (during reset low) by tying clkdbl to gnd, otherwise it is connected to v ddext for 1 ? clock mode. for example, this enables the use of a 27.5 mhz crystal to enable 110 mhz core clock rates and a 55 mhz clkout operation when clk_cfg0=0, clk_cfg1=0 and clkdbl =0. this pin can also be used to generate different clock rate ratios for external clock oscillators as well. the possible clock rate ratio options (up to 110 mhz) for eith er clkin (external clock oscillator) or xtal (crystal input) are shown in table 3 on page 16 . an 8:1 ratio enables the use of a 12.5 mhz crystal to generate a 100 mhz core (instruction clock) rate and a 25 mhz clkout (external port) clock rate. see also figure 8 on page 20 . note: when using an external crystal, the maximum crystal frequency cannot exceed 27.5 mhz. for all other external clock sources, the maximum clkin frequency is 55 mhz. clkout o/t local clock out . clkout is 1 ? or 2 ? and is driven at either 1 ? or 2 ? the frequency of clkin frequency by the current bus master. the frequency is determined by the clkdbl pin. this output is three-stated when the adsp-21161n is not the bus master or when the host controls the bus (hbg asserted). a keeper latch on the dsps clkout pin maintains the output at the level it was last driven. this latch is only enabled on the adsp- 21161n with id2C0=00x. if clkdbl enabled, clkout=2 ?? clkin if clkdbl disabled, clkout=1 ?? clkin note: clkout is only controlled by the clkdbl pin and operates at either 1 ?? clkin or 2 ? clkin. do not use clkout in multiprocessing systems. use clkin instead. reset i/a processor reset . resets the adsp-21161n to a known state and begins execution at the program memory location specified by the hardware reset vector address. the reset input must be asserted (low) at power-up. rstout 1 o reset out . when rstout is asserted (low), this pin indicates that the core blocks are in reset. it is deasserted 4080 cycles after reset is deasserted indicating that the pll is stable and locked. tck i test clock (jtag) . provides a clock for jtag boundary scan. tms i/s test mode select (jtag) . used to control the test state machine. tms has a 20 k ? internal pull-up resistor. tdi i/s test data input (jtag) . provides serial data for the boundary scan logic. tdi has a 20 k ? internal pull-up resistor. tdo o test data output (jtag) . serial scan output of the boundary scan path. trst i/a test reset (jtag) . resets the test state machine. trst must be asserted (pulsed lo w) after power-up or held low for proper operation of the adsp-21161n. trst has a 20 k ? internal pull-up resistor. emu o (o/d) emulation status . must be connected to the adsp-21161n anal og devices dsp tools product line of jtag emulators target board connector only. emu has a 50 k ? internal pull-up resistor. v ddint p core power supply . nominally +1.8 v dc and supplies the dsps core processor (14 pins). v ddext p i/o power supply . nominally +3.3 v dc. (13 pins). avdd p analog power supply . nominally +1.8 v dc and supplies the dsp s internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitry is required. for more information, see power supplies on page 9. agnd g analog power supply return . gnd g power supply return . (26 pins). nc do not connect . reserved pins that must be left open and unconnected. (4 pins) 1 rstout exists only for silicon revisions 1.2 and greater. table 2. pin function descriptions (continued) pin type function
rev. c | page 16 of 60 | january 2013 adsp-21161n boot modes table 3. clock rate ratios clkdbl clk_cfg1 clk_cfg0 core:clkin clkin:clkout 10 0 2:1 1:1 10 1 3:1 1 ?? 11 0 4:1 1 ?? 00 0 4:1 1:2 00 1 6:1 1:2 01 0 8:1 1:2 table 4. boot mode selection eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select.) 0 0 1 (input) host processor 0 1 0 (input) serial boot via spi 0 1 1 (input) link port 0 0 0 (input) no booting. processor executes from external memory. 11x (input)reserved
adsp-21161n rev. c | page 17 of 60 | january 2013 specifications operating conditions parameter 1 1 specifications subject to change without notice. description test conditions 100 mhz 110 mhz unit minmax minmax v ddint internal (core) supply voltage 1.71 1.89 1.71 1.89 v av dd analog (pll) supply voltage 1.71 1.89 1.71 1.89 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 v v ih high level input voltage 2 2 applies to input and bid irectional pins: data47C16, addr23C0, ms3C0 , rd , wr , ack, sbts , irq2C0 , flag11C0, hbg , hbr , cs , dmar1 , dmar2 , br6C1 , id2C0, rpba, pa , brst, fsx, dxa, dxb, sclkx, ras , cas , sdwe , sdclk0, lxdat7C0, lxclk, lxack, spiclk, mosi, miso, spids , eboot, lboot, bms , sdcke, clk_cfgx, clkdbl , clkin, reset , trst, tck, tms, tdi. @ v ddext = max 2.0 v ddext +0.5 2.0 v ddext +0.5 v v il low level input voltage 2 @ v ddext = min C0.5 +0.8 C0.5 +0.8 v t case case operating temperature 3 3 see thermal characteristics on page 55 for information on th ermal specifications. C40 +105 C40 +125 ? c
rev. c | page 18 of 60 | january 2013 adsp-21161n electrical characteristics parameter description test conditions min max unit v oh high level output voltage 1 @ v ddext = min, i oh = C2.0 ma 2 2.4 v v ol low level output voltage 1 @ v ddext = min, i ol = 4.0 ma 2 0.4 v i ih high level input current 3, 4 @ v ddext = max, v in = v ddext max 10 a i il low level input current 3 @ v ddext = max, v in = 0 v 10 a i ihc clkin high level input current 5 @ v ddext = max, v in = v ddext max 35 a i ilc clkin low level input current 5 @ v ddext = max, v in = 0 v 35 a i ikh keeper high load current 6 @ v ddext = max, v in = 2.0 v C250 C100 a i ikl keeper low load current 6 @ v ddext = max, v in = 0.8 v 50 200 a i ikh-od keeper high overdrive current 6, 7, 8 @ v ddext = max C300 a i ikl-od keeper low overdrive current 6, 7, 8 @ v ddext = max 300 a i ilpu low level input current pull-up 4 @ v ddext = max, v in = 0 v 350 a i ozh three-state leakage current 9, 10, 11 @ v ddext = max, v in = v ddext max 10 a i ozl three-state leakage current 9, 12, 13 @ v ddext = max, v in = 0 v 10 a i ozlpu1 three-state leakage current pull-up1 10 @ v ddext = max, v in = 0 v 500 a i ozlpu2 three-state leakage current pull-up2 11 @ v ddext = max, v in = 0 v 350 a i ozhpd1 three-state leakage current pull-down1 12 @ v ddext = max, v in = v ddext max 350 a i ozhpd2 three-state leakage current pull-down2 13 @ v ddext = max, v in = v ddext max 500 a i dd-inpeak supply current (internal) 14, 15 t cclk = 9.0 ns, v ddint = max t cclk = 10.0 ns, v ddint = max 965 900 ma i dd-inhigh supply current (internal) 15, 16 t cclk = 9.0 ns, v ddint = max t cclk = 10.0 ns, v ddint = max 700 650 ma i dd-inlow supply current (internal) 15, 17 t cclk = 9.0 ns, v ddint = max t cclk = 10.0 ns, v ddint = max 535 500 ma i dd-idle supply current (idle) 15, 18 t cclk = 9.0 ns, v ddint = max t cclk = 10.0 ns, v ddint = max 425 400 ma ai dd supply current (analog) 19 @ av dd = max 10 ma c in input capacitance 20, 21 f in = 1 mhz, t case = 25c, v in = 1.8 v 4.7 pf 1 applies to output and bidirectio nal pins: data47C16, addr23C0, ms3C0 , rd , wr , ack, dqm, flag11C0, hbg , redy, dmag1 , dmag2, br6C1 , bmstr, pa , brst, fsx, dxa, dxb, sclkx, ras , cas , sdwe , sda10, lxdat7C0, lxclk, lxack, spiclk, mosi, miso, bms , sdclkx, sdcke, emu , xtal, tdo, clkout, timexp, rstout . 2 see output drive currents on page 54 for typical drive current capabilities. 3 applies to input pins: da ta47C16, addr23C0, ms3C0 , sbts , irq2C0 , flag11C0, hbg , hbr , cs , br6C1 , id2C0, rpba, brst, fsx, dxa, dxb, sclkx, ras , cas , sdwe , sdclk0, lxdat7C0, lxclk, lxack, spiclk, mosi, miso, spids , eboot, lboot, bms , sdcke, clk_cfgx, clkdbl , tck, reset , clkin. 4 applies to input pins with 20 k ? internal pull-ups: rd , wr , ack, dmar1 , dmar2 , pa , trst , tms, tdi. 5 applies to clkin only. 6 applies to all pins with keeper latches: addr23C0, data47C0, ms3C0 , brst, clkout. 7 current required to switch from kept h igh to low or from kept low to high. 8 characterized, but not tested. 9 applies to three-statable pins: data47C16, addr23C0, ms3C0 , clkout, flag11C0, redy, hbg , bms , br6C1 , ras , cas , sdwe , dqm, sdclkx, sdcke, sda10, brst. 10 applies to three-statable pins with 20 k ?? pull-ups: rd , wr , dmag1 , dmag2 , pa . 11 applies to three-statable pins with 50 k ? internal pull-ups: dxa, dxb, sclkx, spiclk., emu , miso, mosi. 12 applies to three-statable pins with 50 k ? internal pull-downs: lxdat7C0 (below revision1.2), lxclk, lxack. use i ozhpd2 for rev. 1.2 and higher. 13 applies to three-statable pins with 20 k ? internal pull-downs: lxdat7-0 (revision 1.2 and higher). 14 the test program used to measure i ddinpeak represents worst-case processor operatio n and is not sustainable under normal appl ication conditions. ac tual internal power measurements made using ty pical applications are less than specified. for more information, see power dissipation on page 20. 15 current numbers are for v ddint and avdd supplies combined. 16 i ddinhigh is a composite average based on a range of high activity code. for more information, see po wer dissipation on page 20. 17 i ddinlow is a composite average based on a range of low activity code. for more information, see po wer dissipation on page 20. 18 idle denotes adsp-21161n state duri ng execution of idle instruction. for more information, see po wer dissipation on page 20. 19 characterized, but not tested. 20 applies to all signal pins. 21 guaranteed, but not tested.
adsp-21161n rev. c | page 19 of 60 | january 2013 package information the information presented in figure 7 provides details about how to read the package brand and relate it to specific product features. absolute maximum ratings stresses greater than those listed in table 6 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution timing specifications the adsp-21161ns intern al clock switches at higher frequen- cies than the system input cl ock (clkin). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsps internal clock (the clock source for the exte rnal port logic and i/o pads). the adsp-21161ns internal clock (a multiple of clkin) pro- vides the clock signal for timi ng internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchrono us access mode). during reset, program the ratio between the dsps internal clock frequency and external (clkin) clock frequency with the clk_cfg1C0 and clkdbl pins. even though the internal clock is the clock source for the external port, it behaves as described in the clock rate ratio chart in table 3 on page 16 . to determine switching frequencies for the serial and link ports, divide down the inter- nal clock, using the programmable divider control of each port (divx for the serial ports and lxclkd for the link ports). note the following definitions of various clock periods that are a function of clkin and the appropriate ratio control ( table 7 ). figure 8 enables core-to-clkin ratios of 2:1, 3:1, 4:1, 6:1, and 8:1 with external osci llator or crystal. it also shows support for clkout-to-clkin ratios of 1:1 and 2:1. use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 37 on page 54 under test conditions for voltage ref- erence levels. switching characteristics specif y how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the proc essor will do in a given circum- stance. use switching characterist ics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to si gnals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. figure 7. typical package brand table 5. package brand information brand key field description adsp-21161n model number ttemperature range pp package type z rohs compliance option vvvvv.x assembly lot code n.n silicon revision # rohs compliance designation yyww date code table 6. absolute maximum ratings parameter rating internal (core) supply voltage (v ddint ) C0.3 v to +2.2 v analog (pll) supply voltage (a vdd ) C0.3 v to +2.2 v external (i/o) supply voltage (v ddext ) C0.3 v to +4.6 v input voltage C0.5 v to v ddext + 0.5 v output voltage swing C0.5 v to v ddext + 0.5 v load capacitance 200 pf storage temperature range C65 ? c to +150 ? c vvvvvv.x n.n s a #yyww country_of_origin adsp-21161n tppz-cc esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality.
rev. c | page 20 of 60 | january 2013 adsp-21161n power dissipation total power dissipation has two components: one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation depend s on the instruction execution sequence and the data operands involved. using the current specifications (i ddinpeak , i ddinhigh , i ddinlow , i ddidle ) from the electrical characteristics on page 18 and the current-versus- operation information in table 8 , the programmer can estimate the adsp-21161ns internal power supply (v ddint ) input cur- rent for a specific applicatio n, according to the following formula: % peak ? i dd - inpeak % high ? i dd - inhigh % low ? i dd - inlow + % peak ? i dd - idle = i ddint figure 8. core clock and system clock relationship to clkin table 7. clkout and cclk clock generation operation timing requirements description 1 calculation clkin input clock 1/t ck clkout external port system clock 1/t ckop plliclk pll input clock 1/t pllin cclk core clock 1/t cclk t ck clkin clock period 1/clkin t cclk (processor) core clock period 1/cclk t lclk link port clock period (t cclk ) ?? lr t sclk serial port clock period (t cclk ) ? sr t sdk sdram clock period (t cclk ) ? sdckr t spiclk spi clock period (t cclk ) ? spir 1 where: lr = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by lxclkd) sr = serial port-to-core clock rati o (wide range, determined by clkdiv) sdckr = sdram-to-core clock ratio (1:1 or 1:2, determined by sdctl register) spir = spi-to-core clock ratio (wide range, determined by spictl register) lclk = link port clock sclk = serial port clock sdk = sdram clock spiclk = spi clock clock doubler x 1, x 2 ratio s x 2, x 3 , x 4 pll a s ynchronou s ep ho s t s ram s ynchronou s ep multiproce ss ing s b s ram hardware interrupt i/o flag timer p l l i c l k ( 4 . 2 C 5 0 m h z ) clkdbl clkout clk_cfg1C0 clkin (cry s tal o s cillator 4.2C55 mhz) xtal (quartz cry s tal 27.5 mhz max) core i/o proce ss or s pi x 1/ 8 max s erial port s x 1/2 max s dram x 1, x 1/2 link port s x 1, x 1/2, x 1/ 3 , x 1/4 c c l k ( 3 3 . 3 C 1 1 0 m h z )
adsp-21161n rev. c | page 21 of 60 | january 2013 the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? the number of output pins th at switch during each cycle ( o ) ? the maximum frequency at which they can switch ( f ) ? their load capacitance ( c ) ? their voltage swing ( v dd ) and is calculated by: the load capacitance should include the processor package capacitance (c in ). the switching frequency includes driving the load high and then back low. at a maximum rate of 1/t ck , address and data pins can drive high and low, while writing to a sdram memory. example: estimate p ext with the following assumptions: ? a system with one bank of external memory (32 bit) ?two 1m 16 sdram chips are used, each with a load of 10 pf (ignoring trace capacitance) ? external data memory writes can occur every cycle at a rate of 1/t ck with 50% of the pins switching ? the bus cycle time is 55 mhz ? the external sdram clock rate is 110 mhz ? ignoring sdram refresh cycles ? addresses are incrementa l and on the same page the p ext equation is calculated for each class of pins that can drive, as shown in table 9 . a typical power consum ption can now be calculated for these conditions by adding a typical internal power dissipation: where: p ext is from table 9 . p int is i ddint 1.8 v, using the calculation i ddint listed in power dissipation on page 20 . p pll is ai dd 1.8 v, using the value for ai dd listed in the electri- cal characteristics on page 18 . note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pi ns are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. table 8. operation types versus input current operation peak activity 1 (i ddinpeak )high activity 1 (i ddinhigh )low activity 1 (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 2 per t ck cycle (dm ? 64 and pm ? 64) 1 per t ck cycle (dm ? 64) none internal memory dma 1 per 2 t cclk cycles 1 per 2 t cclk cycles n/a external memory dma 1 per external port cycle ( ? 32) 1 per external port cycle ( ? 32) n/a data bit pattern for core memory access and dma worst case random n/a 1 the state of the peyen bit (simd versus sisd mode) does not influenc e these calculations. 2 these assume a 2:1 core clock ratio. for more information on ratios and clocks (t ck and t cclk ), see the timing ratio definitions on page 19 . p ext oc ? v dd 2 ? f ? = p total p ext p int p pll ++ = table 9. external power calcul ations110 mhz instruction rate pin type number of pins % switching c f v dd 2 = p ext address 11 20 24.7 pf 55 mhz 10.9 v = 0.033 w msx 4 0 24.7 pf n/a 10.9 v = 0.000 w sdwe 1 0 24.7 pf n/a 10.9 v = 0.000 w data 32 50 14.7 pf 55 mhz 10.9 v = 0.141 w sdclk0 1 100 24.7 pf 110 mhz 10.9 v = 0.030 w p ext = 0.204 w
rev. c | page 22 of 60 | january 2013 adsp-21161n power-up sequencing silicon revision 1.2 and greater the timing requirements fo r dsp startup are given in table 10 . during the power-up sequence of the dsp, differences in the ramp-up rates and activation time between the two supplies can cause current to flow in the i/o esd protection circuitry. to prevent damage to the esd diode protection circuitry, analog devices recommends including a bootstrap schottky diode. the bootstrap schottky diode is connected between the 1.8 v and 3.3 v power supplies as shown in figure 9 . it protects the adsp-21161n from pa rtially powering the 3.3 v supply. including a schottky diode will shorten the delay between the supply ramps and thus prevent damage to the esd diode protection circuitry. with this technique, if the 1.8 v rail rises ahead of the 3.3 v rail, the scho ttky diode pulls the 3.3 v rail along with the 1.8 v rail. figure 9. dual voltage schottky diode 3 . 3 v i/o voltage regulator 1. 8 vcore voltage regulator v ddext v ddint ad s p-21161n dc input s ource table 10. power-up sequencing silicon revi sion 1.2 and greater (dsp startup) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd clkin valid after v ddint /v ddext valid 1 0200ms t clkrst clkin valid before reset deasserted 2 10 s t pllrst pll control setup before reset deasserted 3 20 s t wrst subsequent reset low pulsewidth 4 4t ck ns switching requirements t corerst dsp core reset deasserted after reset deasserted 4080t ck 3, 5 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.8 and 3.3 vo lt rails. voltage ramp rates ca n vary from microseconds to h undreds of milliseconds depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case start-up timing of crystal oscillators. refer to the crystal oscillator manufacturer's data sh eet for start-up time. assume a 25 ms maximum oscillator start-up ti me if using the xtal pin and internal osci llator circuit in conjunction with an ex ternal crystal. 3 based on clkin cycles. 4 applies after the power-up sequence is complete. subseque nt resets require a minimum of 4 clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 5 the 4080 cycle count depends on t srst specification in table 12 . if setup time is not met, one additional clkin cycle may be added to the core reset time, resulting in 4081 cycles maximum. figure 10. power-up sequenci ng for silicon revision 1. 2 and greater (dsp startup) reset rstout clkdbl clk_cfg1-0 clkin t r s tvdd vddext vddint t pllr s t t clkr s t t clkvdd t ivddevdd t corer s t
adsp-21161n rev. c | page 23 of 60 | january 2013 clock input in systems that use multiprocessing or sbsram, clkdbl can- not be enabled nor can the systems use an external crystal as the clkin source. do not use clkout as the clock source for the sbsram device. using an external crystal in conjunction with clkdbl to generate a clkout frequency is not supported. negative hold times can result from the potential skew between clkin and clkout. table 11. clock input parameter 100 mhz 110 mhz unit min max min max timing requirements t ck clkin period 1 20 238 18 238 ns t ckl clkin width low 1 7.5 119 7 119 ns t ckh clkin width high 1 7.5 119 7 119 ns t ckrf clkin rise/fall (0.4 vC2.0 v) 3 3 ns t cclk cclk period 10 30 9 30 ns switching characteristics t dckoo clkout delay after clkin 0 2 0 2 ns t ckop clkout period t ck C1 t ck +1 t ck C1 t ck +1 ns t ckwh clkout width high t ckop /2C2 t ckop /2+2 t ckop /2C2 t ckop /2+2 ns t ckwl clkout width low t ckop /2C2 t ckop /2+2 t ckop /2C2 t ckop /2+2 ns 1 clkin is dependent on the config uration of the clkcfgx and clkdbl pins to achieve desired t cclk . figure 11. clock input clkin t ckh t ck t ckl clkout t dckoo 1 t ckop 1 t ckwl 1 t ckwh 1 clkout note s : 1. when clkdbl i s di s abled, any s pecification to clkin applie s to the ri s ing edge, only. 2. when clkdbl i s enabled, any s pecification to clkin applie s to the ri s ing or falling edge. t dckoo 2 t ckop 2 t dckoo 2 t ckwh 2 t ckwl 2
rev. c | page 24 of 60 | january 2013 adsp-21161n clock signals the adsp-21161n can use an extern al clock or a crystal. see clkin pin description. the pr ogrammer can configure the adsp-21161n to use its internal clock generator by connecting the necessary components to clkin and xtal. figure 12 shows the component connections used for a crystal operating in fundamental mode. reset figure 12. 100 mhz operation (fundamental mode crystal) table 12. reset parameter min max unit timing requirements t wrst reset pulsewidth low 1 1 applies after the power-up sequence is complete. 4t ck ns t srst reset setup before clkin high 2 2 only required if multiple adsp-21161ns must come out of reset synchronous to clkin with program counters (pc) equal. not requir ed for multiple adsp-21161ns communicating over the shared bus (through the external port), because the bus arbitra tion logic synchronizes itself automatica lly after reset. 8.5 ns figure 13. reset clkin xtal c2 27pf c1 27pf x1 s ugge s ted component s for 100mhz operation: ecliptek ec2 s m-25.000m ( s urface mount package) ecliptek ec-25.000m (through-hole package) c1 = 27pf c2 = 27pf note: c1 and c2 are s pecific to cry s tal s pecified for x1. contact cry s tal manufacturer for detail s . thi s 25mhz cry s tal generate s a 100mhz cclk and a 50mhz ep clock with clkdbl enabled and a 2:1 pll multiply ratio. reset clkin t wr s t t s r s t
adsp-21161n rev. c | page 25 of 60 | january 2013 interrupts timer table 13. interrupts parameter min max unit timing requirements t sir irq2C0 setup before clkin 1 6ns t hir irq2C0 hold after clkin 1 0ns t ipw irq2C0 pulsewidth 2 t ckop + 2 ns 1 only required for irqx recognition in the following cycle. 2 applies only if t sir and t hir requirements are not met. figure 14. interrupts clkin t ipw t s ir t hir irq2C0 table 14. timer parameter min max unit switching characteristic t dtex cclk to timexp 1 7 ns figure 15. timer cclk timexp t dtex t dtex
rev. c | page 26 of 60 | january 2013 adsp-21161n flags table 15. flags 100 mhz 110 mhz parameter min max min max unit timing requirement t sfi flag11C0 in setup before clkin 1 44ns t hfi flag11C0 in hold after clkin 1 11ns t dwrfi flag11C0 in delay after rd /wr low 1 12 9 ns t hfiwr flag11C0 in hold after rd /wr deasserted 1 00ns switching characteristics t dfo flag11C0 out delay after clkin 9 9 ns t hfo flag11C0 out hold after clkin 1 1 ns t dfoe clkin to flag11C0 out enable 1 1 ns t dfod clkin to flag11C0 out disable 5 5 ns 1 flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cycl e n+2. figure 16. flags clkin flag11C0 out flag output clkin flag input flag11C0 in t dfo t hfo t dfo t dfod t dfoe t s fi t hfi t hfiwr t dwrfi ,
adsp-21161n rev. c | page 27 of 60 | january 2013 memory read bus master use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped periph erals) without reference to clkin except for ack pin requirements listed in footnote 4 of table 16 . these specifications appl y when the adsp-21161n is the bus master accessing extern al memory space in asynchro- nous access mode. table 16. memory read bus master 100 mhz 110 mhz parameter min max min max unit timing requirements t dad address, selects delay to data valid 1, 2, 3 t ckop C0.25t cclk C8.5+w t ckop C0.25t cclk C6.75+w ns t drld rd low to data valid 1,3 0.75t ckop C11+w 0.75t ckop C11+w ns t hda data hold from address, selects 4 00ns t sds data setup to rd high88ns t hdrh data hold from rd high 4 11ns t daak ack delay from address, selects 2, 5 t ckop C0.5t cclk C12+w t ckop C0.5t cclk C12+w ns t dsak ack delay from rd low 5 t ckop C0.75t cclk C11+w t ckop C0.75t cclk C11+w ns t sakc ack setup to clkin 5 0.5t cclk +3 0.5t cclk +3 ns t hakc ack hold after clkin 1 1 ns switching characteristics t drha address selects hold after rd high 0.25t cclk C1+h 0.25t cclk C1+h ns t darl address selects to rd low 2 0.25t cclk C3 0.25t cclk C3 ns t rw rd pulsewidth t ckop C0.5t cclk C1+w t ckop C0.5t cclk C1+w ns t rwr rd high to wr , rd , dmagx low 0.5t cclk C1+hi 0.5t cclk C1+hi ns w = (number of wait states specified in wait register) t ckop . hi = t ckop (if an address hold cycle or bus idle cycle occurs , as specified in wait register; otherwise hi = 0). h = t ckop (if an address hold cycle occurs as spec ified in wait register; otherwise h = 0). 1 data delay/setup: user must meet t dad , t drld , or t sds. 2 the falling edge of ms x, bms is referenced. 3 the maximum limits of timing requirement values for t dad and t drld parameters are applicable for th e case where ack is always high. 4 data hold: user must meet t hda or t hdrh in asynchronous access mode. see example system hold time calculation on page 54 for the calculation of hold times given capacitive and dc loads. 5 for asynchronous access, ack is sampled only after the programmed wait states for the access have been counted. for the first c lkin cycle of a new external memory access, ack must be driven low (deasserted) by t daak , t dsak , or t sakc . for the second and subsequent cycles of an asynchronous externa l memory access, the t sakc and t hakc must be met for both assertion and deassertion of ack signal.
rev. c | page 28 of 60 | january 2013 adsp-21161n figure 17. memory read bus master ack data t darl t rw t dad t daak t hdrh t hda t rwr t drld t drha t d s ak t s d s t s akc t hakc clkin addre ss msx , bms rd wr , dmag
adsp-21161n rev. c | page 29 of 60 | january 2013 memory write bus master use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped periph erals) without reference to clkin except for ack pin requirements listed in footnote 1 of table 17 . these specifications appl y when the adsp-21161n is the bus master accessing extern al memory space in asynchro- nous access mode. table 17. memory write bus master parameter min max unit timing requirements t daak ack delay from address, selects 1, 2 t ckop C0.5t cclk C12+w ns t dsak ack delay from wr low 1 t ckop C0.75t cclk C11+w ns t sakc ack setup to clkin 1 0.5t cclk +3 ns t hakc ack hold after clkin 1 1ns switching characteristics t dawh address, selects to wr deasserted 2 t ckop C0.25t cclk C3+w ns t dawl address, selects to wr low 2 0.25t cclk C3 ns t ww wr pulsewidth t ckop C0.5t cclk C1+w ns t ddwh data setup before wr high t ckop C0.25t cclk C13.5+w ns t dwha address hold after wr deasserted 0.25t cclk C1+h ns t dwhd data hold after wr deasserted 0.25t cclk C1+h ns t datrwh data disable after wr deasserted 3 0.25t cclk C 2+h 0.25t cclk +2.5+h ns t wwr wr high to wr , rd , dmagx low 0.5t cclk C1.25+hi ns t ddwr data disable before wr or rd low 0.25t cclk C3+i ns t wde wr low to data enabled C0.25t cclk C1 ns w = (number of wait states specified in wait register) t ckop . h = t ckop (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). hi = t ckop (if an address hold cycle or bus idle cycle occurs , as specified in wait register; otherwise hi = 0). i = t ckop (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). 1 for asynchronous access, ack is sampled only after the programmed wait states for the access have been counted. for the first c lkin cycle of a new external memory access, ack must be driven low (deasserted) by t daak , t dsak , or t sakc . for the second and subsequent cycles of an asynchronous externa l memory access, the t sakc and t hakc must be met for both assertion and deassertion of ack signal. 2 the falling edge of msx , bms is referenced. 3 see example system hold time calculation on page 54 for calculation of hold times given capacitive and dc loads.
rev. c | page 30 of 60 | january 2013 adsp-21161n figure 18. memory write bus master t datrwh ack data t dawl t ww t daak t wwr t wde t ddwr t dwha t dawh t d s ak t ddwh t dwhd t s akc t hakc clkin addre ss msx , bms wr rd , dmag
adsp-21161n rev. c | page 31 of 60 | january 2013 synchronous read/write bus master use these specifications for interfacing to external memory sys- tems that require clkin, relative to timing or for accessing a slave adsp-21161n (in multipro cessor memory space). when accessing a slave adsp-21161n, th ese switching characteristics must meet the slave's timing requirements for synchronous read/writes (see synchronous read/wri te bus slave on page 32 ). the slave adsp-21161n must also meet these (bus master) timing requirements fo r data and acknowledge setup and hold times. table 18. synchronous read /write bus master parameter min max unit timing requirements t ssdati data setup before clkin 5.5 ns t hsdati data hold after clkin 1 ns t sackc ack setup before clkin 0.5t cclk +3 ns t hackc ack hold after clkin 1 ns switching characteristics t daddo address, msx , bms , brst, delay after clkin 10 ns t haddo address, msx , bms , brst, hold after clkin 1.5 ns t drdo rd high delay after clkin 0.25t cclk C1 0.25t cclk +9 ns t dwro wr high delay after clkin 0.25t cclk C1 0.25t cclk +9 ns t drwl rd /wr low delay after clkin 0.25t cclk C1 0.25t cclk +9 ns t ddato data delay after clkin 12.5 ns t hdato data hold after clkin 1.5 ns figure 19. synchronous read/write bus master clkin ack (in) data (out) data (in) write cycle read cycle t h s dati t ss dati t drdo t dwro t hdato t ddato t s ackc t hackc t haddo t daddo addre ss msx , br s t rd wr t drwl t drwl
rev. c | page 32 of 60 | january 2013 adsp-21161n synchronous read/write bus slave use these specifications for adsp-21161n bus master accesses of a slaves iop registers in mu ltiprocessor memory space. the bus master must meet these (bus slave) timing requirements. table 19. synchronous read/write bus slave parameter min max unit timing requirements t saddi address, brst setup before clkin 5 ns t haddi address, brst hold after clkin 1 ns t srwi rd /wr setup before clkin 5 ns t hrwi rd /wr hold after clkin 1 ns t ssdati data setup before clkin 5.5 ns t hsdati data hold after clkin 1 ns switching characteristics t ddato data delay after clkin 12.5 ns t hdato data hold after clkin 1.5 ns t dackc ack delay after clkin 10 ns t hacko ack hold after clkin 1.5 ns figure 20. synchronous read/write bus slave clkin addre ss ack data (out) write acce ss data (in) read acce ss t s addi t haddi t dackc t hacko t hrwi t s rwi t ddato t hdato t s rwi t hrwi t h s dati t ss dati rd wr
adsp-21161n rev. c | page 33 of 60 | january 2013 host bus request use these specifications for asyn chronous host bus requests of an adsp-21161n (hbr , hbg ). table 20. host bus request 100 mhz 110 mhz parameter min max min max unit timing requirements t hbgrcsv hbg low to rd /wr /cs valid 19 19 ns t shbri hbr setup before clkin 1 66ns t hhbri hbr hold after clkin 1 11ns t shbgi hbg setup before clkin 6 6 ns t hhbgi hbg hold after clkin 1 1 ns switching characteristics t dhbgo hbg delay after clkin 7 7 ns t hhbgo hbg hold after clkin 1.5 1.5 ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 2 10 10 ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 2 t ckop + 14 t ckop + 12 ns t ardytr redy (a/d) disable from cs or hbr high 2 11 11 ns 1 only required for recognition in the current cycle. 2 (o/d) = open drain, (a/d) = active drive.
rev. c | page 34 of 60 | january 2013 adsp-21161n figure 21. host bus request re d y (o/d) re d y (a/d) o/d = open drain, a/d = active drive t drdyc s t hbgrc s v t trdyhg t ardytr t s hbgi t hhbgi clkin (ou t ) hb g t hhbri t s hbri t hhbgo t dhbg o hb r (in ) hb g hb r cs (ou t ) hb g rd wr cs
adsp-21161n rev. c | page 35 of 60 | january 2013 multiprocessor bus request use these specifications for passi ng of bus mastership between multiprocessing adsp-21161ns (brx ). table 21. multiprocessor bus request parameter min max unit timing requirements t sbri brx setup before clkin high 9 ns t hbri brx hold after clkin high 0.5 ns t spai pa setup before clkin high 9 ns t hpai pa hold after clkin high 1 ns t srpbai rpba setup before clkin high 6 ns t hrpbai rpba hold after clkin high 2 ns switching characteristics t dbro brx delay after clkin high 8 ns t hbro brx hold after clkin high 1.0 ns t dpaso pa delay after clkin high, slave 8 ns t trpas pa disable after clkin high, slave 1.5 ns t dpamo pa delay after clkin high, master 0.25t cclk +9 ns t patr pa disable before clkin high, master 0.25t cclk C5 ns figure 22. multiprocessor bus request t hbri rp ba o/d = op en drai n t hr p b ai t s rpbai t s bri clkin pa (out) ( s la v e) t dbro t hbro t dp a s o t trpa s pa (out) (ma s ter) t dpamo t patr pa (in) (o/d) t hpai t s pa i brx (out) br x (in)
rev. c | page 36 of 60 | january 2013 adsp-21161n asynchronous read/write host to adsp-21161n use these specifications for asynchronous host processor accesses of an adsp-21161n, afte r the host has asserted cs and hbr (low). after hbg is returned by the adsp-21161n, the host can drive the rd and wr pins to access the adsp-21161ns iop registers. hbr and hbg are assumed low for this timing. although the dsp will recognize hbr asserted before reset, a hbg will not be returned by the dsp until after reset is deasserted and the ds p completes bus synchronization. note : host internal memory ac cess is not supported. table 22. read cycle parameter min max unit timing requirements t sadrdl address setup and cs low before rd low 0 ns t hadrdh address hold and cs hold low after rd 2ns t wrwh rd /wr high width 3.5 ns t drdhrdy rd high delay after redy (o/d) disable 0 ns t drdhrdy rd high delay after redy (a/d) disable 0 ns switching characteristics t sdatrdy data valid before redy disable from low 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rd low 10 ns t rdyprd redy (o/d) or (a/d) low pulsewidth for read 1.5t cclk ns t hdarwh data disable after rd high 26ns table 23. write cycle parameter min max unit timing requirements t scswrl cs low setup before wr low 0 ns t hcswrh cs low hold after wr high 0 ns t sadwrh address setup before wr high 6 ns t hadwrh address hold after wr high 2 ns t wwrl wr low width t cclk ?? ns t wrwh rd /wr high width 3.5 ns t dwrhrdy wr high delay after redy (o/d) or (a/d) disable 0 ns t sdatwh data setup before wr high 5 ns t hdatwh data hold after wr high 4 ns switching characteristics t drdywrl redy (o/d) or (a/d) low delay after wr /cs low 1 11 ns t rdypwr redy (o/d) or (a/d) low pulsewidth for write 1 12 ns 1 only when slave write fifo is full.
adsp-21161n rev. c | page 37 of 60 | january 2013 figure 23. asynchronous read/write host to adsp-21161n redy (o/d) read cycle data (out) red y (a /d ) o/d = open drain, a/d = active drive redy (o/d) wr ite c y cle da t a ( in ) addre ss redy (a/d) t drdyrdl t hdarwh t r dyprd t drdhrdy t s dat rdy t s datwh t hdatwh t drdywrl t hadw rh t rdypw r t dwrhrdy t s adwrh t s c s wrl t hc s wrh t hadrdh t wrwh t wwrl t wrwh t s adrdl rd cs wr addre ss / cs
rev. c | page 38 of 60 | january 2013 adsp-21161n three-state timing bus master, bus slave these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin and the sbts pin. this timing is applicable to bus master transi- tion cycles (btc) and host transi tion cycles (htc) as well as the sbts pin. during reset, the dsp will not respond to sbts , hbr , and mms accesses. although the dsp will recognize hbr asserted before reset, a hbg will not be returned by the dsp until after reset is deasserted and the dsp comp letes bus synchronization. table 24. three-state timing bus master, bus slave parameter min max unit timing requirements t stsck sbts setup before clkin 6 ns t htsck sbts hold after clkin 2 ns switching characteristics t miena address/select enable after clkin high 1.5 9 ns t miens strobes enable after clkin high 1 C1.5 +9 ns t mienhg hbg enable after clkin 1.5 9 ns t mitra address/select disable after clkin high 0.5t ckop C20 0.5t ckop C15 ns t mitrs strobes disable after clkin high t ckop C ? 0.25t cclk C17 t ckop C ? 0.25t cclk C12.5 ns t mitrhg hbg disable after clkin 2 0.5t ckop +n ? t cclk C20 0.5t ckop +n ? t cclk C15 ns t daten data enable after clkin 3 1.5 10 ns t dattr data disable after clkin 3 1.5 6 ns t acken ack enable after clkin high 1.5 9 ns t acktr ack disable after clkin high 0.2 5 ns t cdcen clkout enable after clkin 2 0.5t ckop +n ? t cclk 0.5t ckop +n ? t cclk +5 ns t cdctr clkout disable after clkin t ckop C5 t ckop ns t atrhbg address/select disable before hbg low 4 1.5t ckop C6 1.5t ckop +2 ns t strhbg rd /wr /dmagx disable before hbg low 4 t ckop + ? 0.25t cclk C4 t ckop + ? 0.25t cclk +3 ns t btrhbg bms disable before hbg low 4 0.5t ckop C4 0.5t ckop +2 ns t menhbg memory interface enable after hbg high 4 t ckop C5 t ckop +5 ns 1 strobes = rd , wr , dmagx . 2 where n = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively. 3 in addition to bus master transition cycles, these specs al so apply to bus master and bus slave synchronous read/write. 4 memory interface = address, rd , wr , msx , dmagx , and bms (in eprom boot mode). bms is only an output in eprom boot mode.
adsp-21161n rev. c | page 39 of 60 | january 2013 figure 24. three-state timi ng bus master, bus slave clkin ack memory interface clkout t cdctr data memory interface t mitra, t mitr s , t mitrhg t ht s ck t cdcen t miena, t mien s , t mienhg clkin t atrhbg, t s trhbg, t btrhbg t s t s ck t daten t acken t dattr t acktr t menhbg sbts hbg memory interface = addre ss , rd , wr , msx , dmagx , bms (in eprom mode)
rev. c | page 40 of 60 | january 2013 adsp-21161n dma handshake these specifications describe the three dma handshake modes. in all three modes dmar is used to initiate transfers. for hand- shake mode, dmag controls the latching or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr23C0, rd , wr , ms3C0 , ack, and dmag signals. for paced master mode, the data transfer is controlled by addr23C0, rd , wr , ms3C0 , and ack (not dmag ). for paced master mode, the memory read-bus mas- ter, memory write-bus master , and synchronous read/write- bus master timing specifications for addr23C0, rd , wr , ms3C0 , data47C16, and ack also apply. table 25. dma handshake 100 mhz 110 mhz parameter min max min max unit timing requirements t sdrc dmarx setup before clkin 1 3.5 3.5 ns t wdr dmarx width low (nonsynchronous) 2 t cclk +4.5 t cclk +4.5 ns t sdatdgl data setup after dmagx low 3 t ckop C0.5t cclk C7 t ckop C0.5t cclk C7 ns t hdatidg data hold after dmagx high 2 2 ns t datdrh data valid after dmarx high 3 t ckop +3 t ckop +3 ns t dmarll dmarx low edge to low edge 4 t ckop t ckop ns t dmarh dmarx width high 2 t cclk +4.5 t cclk +4.5 ns switching characteristics t ddgl dmagx low delay after clkin 0.25t cclk +1 0.25t cclk +9 0.25t cclk +1 0.25t cclk +9 ns t wdgh dmagx high width 0.5t cclk C1+hi 0.5t cclk C1+hi ns t wdgl dmagx low width t ckop C0.5t cclk C1 t ckop C0.5t cclk C1 ns t hdgc dmagx high delay after clkin t ckop C0.25t cclk +1.0 t ckop C0.25t cclk +9 t ckop C 0.25t cclk +1.0 t ckop C0.25t cclk +9 ns t vdatdgh data valid before dmagx high 5 t ckop C0.25t cclk C8 t ckop C0.25t cclk +5 t ckop C 0.25t cclk C8 t ckop C0.25t cclk +5 ns t datrdgh data disable after dmagx high 6 0.25t cclk C3 0.25t cclk +4 0.25t cclk C3 0.25t cclk +4 ns t dgwrl wrx low before dmagx low C1.5 +2 C1.5 +2 ns t dgwrh dmagx low before wrx high t ckop C0.5t cclk C2+w t ckop C0.5t cclk C2+w ns t dgwrr wrx high before dmagx high 7 C1.5 +2 C1.5 +2 ns t dgrdl rdx low before dmagx low C1.5 +2 C1.5 +2 ns t drdgh rdx low before dmagx high t ckop C0.5t cclk C2+w t ckop C0.5t cclk C2+w ns t dgrdr rdx high before dmagx high 7 C1.5 +2 C1.5 +2 ns t dgwr dmagx high to wrx , rdx low 0.5t cclk C2+hi 0.5t cclk C2+hi ns t dadgh address/select valid to dmagx high 15 13 ns t ddgha address/select hold after dmagx high 11ns w = (number of wait states specified in wait register) ? t ckop . hi = t ckop (if data bus idle cycle occurs, as specified in wait register; otherwise hi = 0). 1 only required for recognition in the current cycle. 2 maximum throughput (@ 110 mhz) using dmarx/dmagx handshaking equals t wdr + t dmarh = (t cclk +4.5) + (t cclk +4.5)=27 ns (37 mhz). this throughput limit applies to non-synchronous access mode only. 3 t sdatdgl is the data setup requirement if dmarx is not being used to hold off completi on of a write. otherwise, if dmarx low holds off completion of the write, the data can be driven t datdrh after dmarx is brought high. 4 use t dmarll if dmarx transitions synchronous with clkin. otherwise, use t wdr and t dmarh . 5 t vdatdgh is valid if dmarx is not being used to hold off completion of a read. if dmarx is used to prolong the read, then t vdatdgh =t ckop C0.25t cclk C8+(nt ckop ) where n equals the number of extra cycles that the access is prolonged. 6 see example system hold time calculation on page 54 for calculation of hold times given capacitive and dc loads. 7 this parameter applies for synchronous access mode only.
adsp-21161n rev. c | page 41 of 60 | january 2013 figure 25. dma handshake clkin t s drc data data t wdr t s drc t dmarh t dmarll t hdgc t wdgh t ddgl t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t s datdgl (external device to external memory) (external memory to external device) tran s fer s between ad s p-21161n internal memory and external device tran s fer s between external device and external memory 1 (external hand s hake mode) t ddgha addre ss msx t dadgh t wdgl (from external drive to ad s p-21161n) (from ad s p-2116x to external drive) t dgwr dmarx dmagx wr rd 1 memory read bu s ma s ter, memory write bu s ma s ter, or s ynchronou s read/write bu s ma s ter timing s pecification s for addr2 3 C0, rd , wr , ms3-0 and ack al s o apply here.
rev. c | page 42 of 60 | january 2013 adsp-21161n sdram interface bus master use these specifications for adsp-21161n bus master accesses of sdram: sdram interface bus slave these timing requirements allow a bus slave to sample the bus masters sdram command and de tect when a refresh occurs: table 26. sdram interface bus master parameter 100 mhz 110 mhz unit min max min max timing requirements t sdsdk data setup before sdclk 2.0 2.0 ns t hdsdk data hold after sdclk 2.3 2.3 ns switching characteristics t dsdk1 first sdclk rise delay after clkin 1, 2 0.75t cclk + 1.5 0.75t cclk + 8.0 0.75t cclk + 1.5 0.75t cclk + 8.0 ns t sdk sdclk period t cclk 2 ? t cclk t cclk 2 ? t cclk ns t sdkh sdclk width high 4 3 ns t sdkl sdclk width low 4 3 ns t dcadsdk command, address, data, delay after sdclk 3 0.25t cclk +2.5 0.25t cclk +2.5 ns t hcadsdk command, address, data, hold after sdclk 3 2.0 2.0 ns t sdtrsdk data three-state after sdclk 4 0.5t cclk + 2.0 0.5t cclk + 2.0 ns t sdensdk data enable after sdclk 5 0.75t cclk 0.75t cclk ns t sdctr command three-state after clkin 0.5t cclk C1.5 0.5t cclk + 6.0 0.5t cclk C1.5 0.5t cclk + 6.0 ns t sdcen command enable after clkin 2 5 2 5 ns t sdsdktr sdclk three-state after clkin 0 3 0 3 ns t sdsdken sdclk enable after clkin 1 4 1 4 ns t sdatr address three-state after clkin ? 0.25 t cclk ? 5 ? 0.25t cclk ? 0.25 t cclk ? 5 ? 0.25t cclk ns t sdaen address enable after clkin ? 0.4 +7.2 ? 0.4 +7.2 ns 1 for the second, third, and fourth rising ed ges of sdclk delay from clkin, add appr opriate number of sdclk period to the t dsdk1 and t ssdkc1 values, depending upon the sdckr value and the core clock to clkin ratio. 2 subtract t cclk from result if value is greater than or equal to t cclk . 3 command = sdcke, msx , dqm, ras , cas , sda10, and sdwe . 4 sdram controller a dds one sdram clk three-stated cycle de lay on a read, followed by a write. 5 valid when dsp transitions to sdram master from sdram slave. table 27. sdram interface bus slave parameter min max unit timing requirements t ssdkc1 first sdclk rise after clkout 1, 2, 3 sdck ? t cclk ?? 0.5t cclk ? 0.5 sdckr ? t cclk ?? 0.25t cclk + 2.0 ns t scsdk command setup before sdclk 4 2ns t hcsdk command hold after sdclk 4 1ns 1 for the second, third, and fourth rising ed ges of sdclk delay from cl kout, add appropriate number of sdclk period to the t dsdk1 and t ssdkc1 values, depending upon the sdckr value and the core clock to clkout ratio. 2 sdckr = 1 for sdclk equal to core cl ock frequency and sdckr = 2 for sdclk equal to half core clock frequency. 3 subtract t cclk from result if value is greater than or equal to t cclk . 4 command = sdcke, ras , cas , and sdwe .
adsp-21161n rev. c | page 43 of 60 | january 2013 figure 26. sdram interface clkin s dclk data(in) data(out) cmnd 1 addr (out) cmnd 1 (out) addr (out) clkout s dclk (in) cmnd 2 (in) t s dk t d s dk1 t s dkh t s dkl t s d s dk t hd s dk t dcad s dk t s den s dk t s dtr s dk t hcad s dk t dcad s dk t hcad s dk t s dcen t s dctr t s datr t s daen t ss dkc1 t s c s dk t hc s dk clkin t s d s dken t s d s dktr s dclk 1 command = s dcke, msx , ras , cas , sdwe ,dqm,and s da10. 2 command = s dcke, ras , cas , and sdwe .
rev. c | page 44 of 60 | january 2013 adsp-21161n link ports calculation of link receiver data setup and hold relative to link clock is required to determin e the maximum allowable skew that can be introduced in the transmission path between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata relative to lclk, (setup skew = t lclktwh min C t dldch C t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata, (hold skew = t lclktwl min C t hldch C t hldcl ). calcula- tions made directly from speed specifications will result in unrealistically small skew times because they in clude multiple tester guardbands. the setup an d hold skew times shown below are calculated to include only one tester guardband. adsp-21161n setup skew = 1.5 ns max adsp-21161n hold skew = 1.5 ns max note that there is a two-cycle effect latency between the link port enable instruction and th e dsp enabling the link port. table 28. link ports receive parameter min max unit timing requirements t sldcl data setup before lclk low 1 ns t hldcl data hold after lclk low 3.5 ns t lclkiw lclk period t lclk ns t lclkrwl lclk width low 4.0 ns t lclkrwh lclk width high 4.0 ns switching characteristics t dlalc lack low delay after lclk high 1 812ns 1 lack goes low with t dlalc relative to rise of lclk after first nibble, but does not go low if the receiv er's link buffer is not about to fill. figure 27. link portsreceive lclk ldat7-0 lack (out) receive in t s ldcl t hldcl t dlalc t lclkrwl t lclkiw t lc lkrwh
adsp-21161n rev. c | page 45 of 60 | january 2013 table 29. link ports transmit parameter min max unit timing requirements t slach lack setup before lclk high 8 ns t hlach lack hold after lclk high C2 ns switching characteristics t dldch data delay after lclk high 3 ns t hldch data hold after lclk high 0 ns t lclktwl lclk width low 0.5t lclk C1.0 0.5t lclk +1.0 ns t lclktwh lclk width high 0.5t lclk C1.0 0.5t lclk +1.0 ns t dlaclk lclk low delay after lack high 0.5t lclk +3 3t lclk +11 ns figure 28. link portstransmit lclk ldat7-0 lack (in) the t s lach requirement applie s to the ri s ing edge of lclk only for the fir s t nibble tran s mitted. tran s mit la s t nibble/byte tran s mitted fir s t nibble/byte tran s mitted lclk inactive (high) out t dldch t hldch t lclktwh t lclktwl t s lach t hlach t dlaclk
rev. c | page 46 of 60 | january 2013 adsp-21161n serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. table 30. serial ports external clock parameter min max unit timing requirements t sfse transmit/receive fs setup before transmit/receive sclk 1 3.5 ns t hfse transmit/receive fs hold after transmit/receive sclk 1 2ns t sdre receive data setup before receive sclk 1 1.5 ns t hdre receive data hold after receive sclk 1 4ns t sclkw sclkx width 7 ns t sclk sclkx period 2t cclk ns 1 referenced to sample edge. table 31. serial ports internal clock parameter min max unit timing requirements t sfsi fs setup time before sclk (transmit/receive mode) 1 8ns t hfsi fs hold after sclk (transmit/receive mode) 1 0.5t cclk +1 ns t sdri receive data setup before sclk 1 4ns t hdri receive data hold after sclk 1 3ns 1 referenced to sample edge. table 32. serial ports external clock parameter 100 mhz 110 mhz unit min max min max switching characteristics t dfse fs delay after sclk (i nternally generated fs) 1, 2, 3 13 13 ns t hofse fs hold after sclk (internally generated fs) 1, 2 , 3 32.75ns t ddte transmit data delay after sclk 1, 2 16 16 ns t hdte transmit data hold after sclk 1, 2 00ns 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. 3 sclk/fs configured as a receive clock/frame s ync with the ddir bit = 0 in spctlx register. table 33. serial ports internal clock parameter min max unit switching characteristics t dfsi fs delay after sclk (internally generated fs) 1, 2, 3 4.5 ns t hofsi fs hold after sclk (internally generated fs) 1, 2, 3 C1.5 ns t ddti transmit data delay after sclk 1, 2 7.5 ns t hdti transmit data hold after sclk 1, 2 0ns t sclkiw sclk width 2 0.5t sclk C2.5 0.5t sclk +2 ns 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. 3 sclk/fs configured as a receive clock/frame s ync with the ddir bit = 0 in spctlx register.
adsp-21161n rev. c | page 47 of 60 | january 2013 table 34. serial ports C enable and three-state parameter min max unit switching characteristics t ddten data enable from external transmit sclk 1, 2 4ns t ddtte data disable from external transmit sclk 1 10 ns t ddtin data enable from internal transmit sclk 1 0ns t ddtti data disable from internal transmit sclk 1 3ns 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. table 35. serial ports external late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external transm it fs or external receive fs with mce = 1, mfd = 0 1 13 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 1 0.5 ns 1 mce = 1, transmit fs enable and transmit fs valid follow t ddtlfse and t ddtenfs .
rev. c | page 48 of 60 | january 2013 adsp-21161n figure 29. serial ports drive edge s clk (int) drive edge s clk drive edge drive edge s clk s clk (ext) t ddtte t ddten t ddtti t ddtin d x a/d x b d x a/d x b s clk f s drive edge s ample edge data receive internal clock data receive external clock s clk f s drive edge s ample edge note: either the ri s ing edge or falling edge of s clk (external), s clk (internal) can be u s ed a s the active s ampling edge. t s dri t hdri t s f s i t hf s i t df s i t hof s i t s clkiw t s dre t hdre t s f s e t hf s e t df s e t s clkw t hof s e d x a/d x b d x a/d x b t ddti s clk f s drive edge s ample edge data tran s mit internal clock t s f s i t hf s i t df s i t hof s i t s clkiw d x a/d x b t hdti note: either the ri s ing edge or falling edge of s clk (external), s clk (internal) can be u s ed a s the active s ampling edge. t ddte s clk f s drive edge s ample edge data tran s mit external clock t s f s e t hf s e t df s e t hof s e t s clkw d x a/d x b t hdte
adsp-21161n rev. c | page 49 of 60 | january 2013 figure 30. serial ports external late frame sync drive s ample drive s clk f s d x a/d x b drive s ample drive late external tran s mit f s external receive f s with mce = 1, mfd = 0 1 s t bit 2nd bit s clk f s 1 s t bit 2nd bit t hof s e/i t s f s e/i t ddte/i t ddtenf s t ddtlf s e t hdte/i t hof s e/i t s f s e/i t ddte/i t ddtenf s t ddtlf s e t hdte/i d x a/d x b
rev. c | page 50 of 60 | january 2013 adsp-21161n spi interface specifications table 36. spi interface protocol master switching and timing 100 mhz 110 mhz unit parameter min max min max timing requirements t sspidm data input valid to spiclk edge (data input set-up time) 0.5t cclk +10 0.5t cclk +10 ns t hspidm spiclk last sampling edge to data input not valid 0.5t cclk +1 0.5t cclk +1 ns switching characteristics t spiclkm serial clock cycle 8t cclk 8t cclk C4 ns t spichm serial clock high period 4t cclk C4 4t cclk C4 ns t spiclm serial clock low period 4t cclk C4 4t cclk C4 ns t ddspidm spiclk edge to data out valid (data out delay time) 3 3 ns t hdspidm spiclk edge to data out not valid (data out hold time) 0 0 ns t sdscim_0 flag3C0 (spi device select) low to first spiclk edge for cphase = 0 5t cclk 5t cclk ns t sdscim_1 flag3C0 (spi device select) low to first spiclk edge for cphase = 1 3t cclk 3t cclk ns t hdsm last spiclk edge to flag3C0 high t cclk C3 t cclk C3 ns t spitdm sequential transfer delay 2t cclk 2t cclk ns figure 31. spi interface protocol master switching and timing l s b valid m s b valid t ss pidm t h s pidm t hd s pidm l s b m s b t h s pidm t dd s pidm mo s i (output) mi s o (input) flag 3 -0 (output) s piclk (cp = 0) (output) s piclk (cp = 1) (output) t s pichm t s piclm t s piclm t s piclkm t s pichm t hd s m t s pitdm t hd s pidm l s b valid l s b m s b m s b valid t h s pidm t dd s pidm mo s i (output) mi s o (input) t ss pidm cpha s e=1 cpha s e=0 t s d s cim t ss pidm
adsp-21161n rev. c | page 51 of 60 | january 2013 table 37. spi interface protocol slave switching and timing parameter min max unit timing requirements t spiclks serial clock cycle 8t cclk ns t spichs serial clock high period 4t cclk C4 ns t spicls serial clock low period 4t cclk C4 ns t sdsco spids assertion to first spiclk edge cphase = 0 3.5t cclk +8 ns cphase = 1 1.5t cclk +8 ns t hds last spiclk edge to spids not asserted cphase = 0 0 ns t sspids data input valid to spiclk edge (data input set-up time) 0 ns t hspids spiclk last sampling edge to data input not valid t cclk +1 ns t sdppw spids deassertion pulsewidth (cphase = 0) t cclk ns switching characteristics t dsoe spids assertion to data out active 2 0.5t cclk +5.5 ns t dsdhi spids deassertion to data high impedance 1.5 0.5t cclk +5.5 ns t ddspids spiclk edge to data out va lid (data out delay time) 0.75t cclk +3 ns t hdspids 1 spiclk edge to data out not valid (data out hold time) 0.25t cclk +3 ns t hdlsbs 1 spiclk edge to last bit out not valid (data out hold time) for lsb 0.5t spiclk +4.5t cclk ns t dsov 2 spids assertion to data out valid (cphase = 0) 1.5t cclk +7 ns 1 when cphase = 0 and baud ra te is greater than 1, t hdlsbs affects the length of the last bit transmitted. 2 applies to the first deassertion of spids only.
rev. c | page 52 of 60 | january 2013 adsp-21161n figure 32. spi interface protocol slave switching and timing t h s pid s t dd s pid s t d s dhi l s b m s b m s bvalid t d s oe t dd s pid s t hd s pid s mi s o (output) mo s i (input) t ss pid s spids (input) s piclk (cp = 0) (input) s piclk (cp = 1) (input) t s d s co t s pich s t s picl s t s picl s t s piclk s t hd s t s pich s t ss pid s t h s pid s t d s dhi l s bvalid m s b m s bvalid t d s oe t dd s pid s mi s o (output) mo s i (input) t ss pid s l s bvalid l s b cpha s e=1 cpha s e=0 t s dppw t d s ov t hd s pid s t hdl s b s
adsp-21161n rev. c | page 53 of 60 | january 2013 jtag test access port and emulation table 38. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck low 1 2ns t hsys system inputs hold after tck low 1 15 ns t trstw trst pulsewidth 4t ck ns switching characteristics t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 2 30 ns 1 system inputs = data47C16, addr23C0, rd , wr , ack, rpba, spids , eboot, lboot, dmar2C1 , clk_cfg1C0, clkdbl , cs , hbr , sbts , id2C0, irq2C0 , reset , bms , miso, mosi, spiclk, dxa, dxb, sclkx, fsx, lxdat7C0, lxclk, lxack, sdwe , hbg , ras , cas , sdclk0, sdcke, brst, br6C1 , pa , ms3C0 , flag11C0. 2 system outputs = bms , miso, mosi, spiclk, dxa, dxb, sclkx, fsx, lxdat7C0, lxclk, lxack, data47C16, sdwe , ack, hbg , ras , cas , sdclk1C0, sdcke, brst, rd , wr , br6C1 , pa , ms3C0 , addr23C0, flag11C0, dmag2C1 , dqm, redy, clkout, sda10, timexp, emu , bmstr, rstout . figure 33. jtag test ac cess port and emulation tck tm s tdi tdo s y s tem input s s y s tem output s t s tap t tck t htap t dtdo t ss y s t h s y s t d s y s
rev. c | page 54 of 60 | january 2013 adsp-21161n output drive currents figure 34 shows typical i-v characteri stics for the output driv- ers of the adsp-21161n. the curv es represent the current drive capability of the output drivers as a function of output voltage. test conditions the dsp is tested for output enable, disable, and hold time. output enable time output pins are considered to be enabled when they have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output has reached a specified high or low trip point, as shown in the output enable/disable dia- gram ( figure 35 ). if multiple pins (suc h as the data bus) are enabled, the measurement value is that of the first pin to start driving. output disable time output pins are considered to be disabled when they stop driv- ing, go into a high-impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the following equation: t decay = (c l ? v)/i l the output disable time t dis is the difference between t measured and t decay as shown in figure 35 . the time t measured is the inter- val from when the reference signal switches to when the output voltage decays ? v from the measured output high or output low voltage. t decay is calculated with test loads c l and i l , and with ? v equal to 0.5 v. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the adsp-21161ns output voltage and the input threshold for the device requiring the hold time. a typical ? v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or th ree-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). figure 34. typical drive currents s weep (v ddext ) voltage C v 60 C10 C40 0 3 .5 0.5 1.0 1.5 2.0 2.5 3 .0 50 0 C20 C 3 0 3 0 10 40 20 C50 C60 l o a d ( v d d e x t ) c u r r e n t C m a v ddext = 3 .47v, C40c v ddext = 3 . 3 v, +25c v ddext = 3 .1 3 v, +105c v ddext = 3 .1 3 v, +105c v ddext = 3 .47v, C40c v ddext = 3 . 3 v, +25c 8 0 C 8 0 figur 35. output en/dis figur 36. euivnt dvic loing for ac msurmnts (incus a fixturs) figur 37. votg rf rnc lvs for ac msurmnts (excpt output en/dis) reference s ignal t di s output s tart s driving v oh (mea s ured) C v v ol (mea s ured) + v t mea s ured v oh (mea s ured) v ol (mea s ured) 2.0v 1.0v v oh (mea s ured) v ol (mea s ured) high impedance s tate. te s tcondition s cau s ethi s voltage to be approximately 1.5v. output s top s driving t ena t decay 1.5v 3 0pf to output pin 50 input or output 1.5v 1.5v
adsp-21161n rev. c | page 55 of 60 | january 2013 capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 36 on page 54 ). figure 38 shows graphically how output delays an d holds vary with load capaci- tance. (note that this graph or de rating does not apply to output disable delays; see output disable time on page 54 .) the graphs of figure 38 , figure 39 , and figure 40 may not be linear outside the ranges shown for typical ou tput delay vs. load capaci- tance and typical output rise time (20% C 80%, v = min) vs. load capacitance. environmental conditions the thermal characteristics in which the dsp is operating influ- ence performance. thermal characteristics the adsp-21161n is packaged in a 225-ball chip scale package ball grid array (csp_bga). the adsp-21161n is specified for a case temperature ( t case ). to ensure that the t case data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. use the center block of ground pins (csp_bga balls: f6-10, g6-10, h6 -10, j6-10, k6-10) to provide thermal pathways to the printed circuit boards ground plane. a heatsink should be a ttached to the ground plane (as close as pos- sible to the thermal pathways) with a thermal adhesive. where: ? t case = case temperature (measured on top surface of package) ? t amb = ambient temperature c ? pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown under power dissipation). ? ? ca = value from table 39 . figure 38. typical output delay or hold vs. load capacitance (at max case temperature) figure 39. typical output rise/fall time (20% C 80%, v ddext = max) figure 40. typical output rise/fall time (20% C 80%, v ddext = min) load capacitance C pf 25 C5 0210 3 0 60 90 120 150 1 8 0 20 15 10 5 nominal y=0.0 83 5x - 2.42 o u t p u t d e l a y o r h o l d C n s load capacitance C pf 16.0 8 .0 0 0 200 20 40 60 8 0 100 120 140 160 1 8 0 14.0 12.0 4.0 2.0 10.0 6.0 fall time ri s etime y = 0.074 3 x+1.561 3 r i s e a n d f a l l t i m e s C n s ( 0 . 6 9 4 v t o 2 . 7 7 v , 2 0 % t o 8 0 % ) y = 0.0414x + 2.012 8 load capacitance C pf 16.0 8 .0 0 0200 20 40 60 8 0 100 120 140 160 1 8 0 14.0 12.0 4.0 2.0 10.0 6.0 fall time ri s etime y=0.077 3 x+1.4 3 99 r i s e a n d f a l l t i m e s C n s ( 0 . 6 9 4 v t o 2 . 7 7 v , 2 0 % t o 8 0 % ) y = 0.0417x + 1. 8 674 table 39. airflow over package versus ? ca airflow (linear ft./min.) 0 200 400 ? ca (c/w) ? jc 1 1 = 6.8c/w. 17.9 15.2 13.7 t case t amb pd ? ca ? ?? + =
rev. c | page 56 of 60 | january 2013 adsp-21161n 225-ball csp_bga ball configurations table 40. 225-ball csp_bga ball assignments ball name ball number ball name ball number ball name ball number ball name ball number nc a01 trst b01 tms c01 tdo d01 bmstr a02 tdi b02 emu c02 tck d02 bms a03 rpba b03 gnd c03 flag11 d03 spids a04 mosi b04 spiclk c04 miso d04 eboot a05 fs0 b05 d0b c05 sclk0 d05 lboot a06 sclk1 b06 d1a c06 d1b d06 sclk2 a07 d2b b07 d2a c07 fs1 d07 d3b a08 d3a b08 fs2 c08 v ddint d08 l0dat4 a09 l0dat7 b09 fs3 c09 sclk3 d09 l0ack a10 l0clk b10 l0dat6 c10 l0dat5 d10 l0dat2 a11 l0dat1 b11 l1dat7 c11 l0dat3 d11 l1dat6 a12 l1dat4 b12 l1dat3 c12 l1dat5 d12 l1clk a13 l1ack b13 l1dat1 c13 data42 d13 l1dat2 a14 l1dat0 b14 data45 c14 data46 d14 nc a15 rstout 1 b15 data47 c15 data44 d15 flag10 e01 flag5 f01 flag1 g01 flag0 h01 reset e02 flag7 f02 flag2 g02 irq0 h02 flag8 e03 flag9 f03 flag4 g03 v ddint h03 d0a e04 flag6 f04 flag3 g04 irq1 h04 v ddext e05 v ddint f05 v ddext g05 v ddint h05 v ddint e06 gnd f06 gnd g06 gnd h06 v ddext e07 gnd f07 gnd g07 gnd h07 v ddint e08 gnd f08 gnd g08 gnd h08 v ddext e09 gnd f09 gnd g09 gnd h09 v ddint e10 gnd f10 gnd g10 gnd h10 v ddext e11 v ddint f11 v ddext g11 v ddint h11 l0dat0 e12 data37 f12 data34 g12 data29 h12 data39 e13 data40 f13 data35 g13 data28 h13 data43 e14 data38 f14 data33 g14 data30 h14 data41 e15 data36 f15 data32 g15 data31 h15 irq2 j01 timexp k01 addr19 l01 addr16 m01 id1 j02 addr22 k02 addr17 l02 addr12 m02 id2 j03 addr20 k03 addr21 l03 addr18 m03 id0 j04 addr23 k04 addr2 l04 addr6 m04 v ddext j05 v ddint k05 v ddext l05 addr0 m05 gnd j06 gnd k06 v ddint l06 ms1 m06 gnd j07 gnd k07 v ddext l07 br6 m07 gnd j08 gnd k08 v ddint l08 v ddext m08 gnd j09 gnd k09 v ddext l09 wr m09 gnd j10 gnd k10 v ddint l10 sda10 m10 v ddext j11 v ddint k11 v ddext l11 ras m11 data26 j12 data22 k12 cas l12 ack m12 data24 j13 data19 k13 data20 l13 data17 m13 data25 j14 data21 k14 data16 l14 dmag2 m14 data27 j15 data23 k15 data18 l15 dmag1 m15
adsp-21161n rev. c | page 57 of 60 | january 2013 addr14 n01 addr13 p01 nc r01 addr15 n02 addr9 p02 addr11 r02 addr10 n03 addr8 p03 addr7 r03 addr5 n04 addr4 p04 addr3 r04 addr1 n05 ms2 p05 ms3 r05 ms0 n06 sbts p06 pa r06 br5 n07 br4 p07 br3 r07 br2 n08 br1 p08 rd r08 brst n09 sdclk1 p09 clkout r09 sdcke n10 sdclk0 p10 hbr r10 cs n11 redy p11 hbg r11 clk_cfg1 n12 clkin p12 clkdbl r12 clk_cfg0 n13 dqm p13 xtal r13 avdd n14 agnd p14 sdwe r14 dmar1 n15 dmar2 p15 nc r15 1 rstout exists only for silicon revisions 1.2 and greater. leave this ball unconnected for silicon revisions 0.3, 1.0, and 1.1. figure 41. 225-ball csp_bga ball assignments (bottom view, summary) table 40. 225-ball csp_bga ball assignments (continued) ball name ball number ball name ball number ball name ball number ball name ball number vddint vddext gnd * agnd avdd s ignal * u s e the center block of ground pin s to provide thermal pathway s to your printed circuit board ground plane key: 1 2 3 4 5 6 7 8 9 10 11 12 14 15 1 3 r p n m l k j h g f e d c b a
rev. c | page 58 of 60 | january 2013 adsp-21161n outline dimensions the adsp-21161n comes in a 17 mm ? 17 mm, 225-ball csp_bga package with 15 rows of balls. surface-mount design table 41 is provided as an aid to pcb design. for industry stan- dard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . ordering guide figure 42. 225-ball csp_bga (bc-225-1) * compliant to jedec standards mo-192-aaf-2 with the exception to package height and thickness. 0.50 ref 17.20 17.00 sq 16.80 ball diameter coplanarity 0.20 1.00 bsc 14.00 bsc sq detail a a1 ball corner a1 ball corner detail a bottom view top view seating plane 0.70 0.60 0.50 0.54 0.50 0.30 * 1.31 1.21 1.10 * 1.85 1.71 1.40 a b c d e f g h j k l m n p r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 table 41. bga data for use with surface-mount design package ball attach type solder mask opening ball pad size 225-ball csp_bga (bc-225-1) solder mask defined 0.40 mm diameter 0.53 mm diameter model 1 1 z = rohs compliant part. temperature range 2 2 referenced temperature is case temperature. instruction rate on-chip sram package description package option adsp-21161nkca-100 0 ? c to 85 ? c 100 mhz 1m bit 225-ball csp_bga bc-225-1 adsp-21161ncca-100 C40 ? c to +105 ? c 100 mhz 1m bit 225-ball csp_bga bc-225-1 adsp-21161nkcaz100 0 ? c to 85 ? c 100 mhz 1m bit 225-ball csp_bga bc-225-1 adsp-21161nccaz100 C40 ? c to +105 ? c 100 mhz 1m bit 225-ball csp_bga bc-225-1 ADSP-21161NYCAZ110 C40 ? c to +125 ? c 110 mhz 1m bit 225-ball csp_bga bc-225-1
adsp-21161n rev. c | page 59 of 60 | january 2013
rev. c | page 60 of 60 | january 2013 adsp-21161n ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02935-0-1/13 (c)

▲Up To Search▲

Price & Availability of ADSP-21161NYCAZ110

	To Download ADSP-21161NYCAZ110 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .